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MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
Order this documentby MC68HC11FTS/D
MC68HC11F1MC68HC11FC0
Technical Summary8-Bit Microcontroller
1 Introduction
The MC68HC11F1 is a high-performance member of the M68HC11 family of microcontroller units(MCUs). High-speed expanded systems required the development of this chip with its extra input/output(I/O) ports, an increase in static RAM (one Kbyte), internal chip-select functions, and a non-multiplexedbus which reduces the need for external interface logic. The timer, serial I/O, and analog-to-digital (A/D) converter enable functions similar to those found in the MC68HC11E9.
The MC68HC11FC0 is a low cost, high-speed derivative of the MC68HC11F1. It does not haveEEPROM or an analog-to-digital converter. The MC68HC11FC0 can operate at bus speeds as high assix MHz.
This document provides a brief overview of the structure, features, control registers, packaging infor-mation and availability of the MC68HC11F1 and MC68HC11FC0. For detailed information onM68HC11 subsystems, programming and the instruction set, refer to the M68HC11 Reference Manual(M68HC11RM/AD).
1.1 Features
• MC68HC11 CPU
• 512 Bytes of On-Chip Electrically Erasable Programmable ROM (EEPROM) with Block Protect(MC68HC11F1 only)
• 1024 Bytes of On-Chip RAM (All Saved During Standby)• Enhanced 16-Bit Timer System— 3 Input Capture (IC) Functions— 4 Output Compare (OC) Functions— 4th IC or 5th OC (Software Selectable)• On-Board Chip-Selects with Clock Stretching• Real-Time Interrupt Circuit• 8-Bit Pulse Accumulator
• Synchronous Serial Peripheral Interface (SPI)
• Asynchronous Nonreturn to Zero (NRZ) Serial Communication Interface (SCI)• Power saving STOP and WAIT Modes
• Eight-Channel 8-Bit A/D Converter (MC68HC11F1 only)
• Computer Operating Properly (COP) Watchdog System and Clock Monitor
• Bus Speeds of up to 6 MHz for the MC68HC11FC0 and up to 5 MHz for the MC68HC11F1
• 68-Pin PLCC (MC68HC11F1 only), -Pin QFP (MC68HC11FC0 only), and 80-pin TQFP pack-age options
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© MOTOROLA INC., 1997
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1.2 Ordering Information
The following devices all have 1024 bytes of RAM. In addition, the MC68HC11F1 devices have 512bytes of EEPROM. None of the devices contain on-chip ROM.
Table 1 MC68HC11F1 Standard Device Ordering Information
Package
Temperature0° to +70°
Frequency5 MHz2 MHz
-40° to +85°C
80-Pin Thin Quad Flat Pack
(TQFP)
(14 mm X 14 mm,1.4 mm thick)
3 MHz4 MHz5 MHz2 MHz
– 40° to + 105° C
3 MHz4 MHz2 MHz
– 40° to + 125° C
0° to +70°
3 MHz4 MHz5 MHz2 MHz
– 40° to + 85° C
3 MHz4 MHz5 MHz
68-Pin PLCC
– 40° to + 105° C
2 MHz3 MHz4 MHz2 MHz
– 40° to + 125° C
3 MHz4 MHz
MC Order NumberMC68HC11F1PU5MC68HC11F1CPU2MC68HC11F1CPU3MC68HC11F1CPU4MC68HC11F1CPU5MC68HC11F1VPU2MC68HC11F1VPU3MC68HC11F1VPU4MC68HC11F1MPU2MC68HC11F1MPU3MC68HC11F1MPU4MC68HC11F1FN5MC68HC11F1CFN2MC68HC11F1CFN3MC68HC11F1CFN4MC68HC11F1CFN5MC68HC11F1VFN2MC68HC11F1VFN3MC68HC11F1VFN4MC68HC11F1MFN2MC68HC11F1MFN3MC68HC11F1MFN4
Table 2 MC68HC11F1 Extended Voltage (3.0 to 5.5 V) Device Ordering Information
Package
68-Pin Plastic Leaded Chip
Carrier (PLCC)80-Pin Thin Quad Flat Pack
(TQFP)
Temperature0° to +70°C–40° to +85°C0° to +70°C–40° to +85°C
Frequency3 MHz3 MHz3 MHz3 MHz
MC Order NumberMC68L11F1FN3MC68L11F1CFN3MC68L11F1PU3MC68L11F1CPU3
MOTOROLA2MC68HC11F1/FC0MC68HC11FTS/D
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Table 3 MC68HC11FC0 Standard Device Ordering Information
Package
-Pin Quad Flat Pack
(QFP)
Temperature–40° to +85°C 0° to 70° C–40° to +85°C 0° to 70° C
Frequency4 MHz5 MHz6 MHz4 MHz5 MHz6 MHz
MC Order NumberMC68HC11FC0CFU4MC68HC11FC0CFU5MC68HC11FC0FU6MC68HC11FC0CPU4MC68HC11FC0CPU5MC68HC11FC0PU6
80-Pin Thin Quad Flat Pack
(TQFP)
Table 4 MC68HC11FC0 Extended Voltage (3.0 to 5.5 V) Device Ordering Information
Package
-Pin Quad Flat Pack
(QFP)80-Pin Thin Quad Flat Pack
(TQFP)
Temperature
Frequency3 MHz
–0° to +70°C
4 MHz3 MHz4 MHz
MC Order NumberMC68L11FC0FU3MC68L11FC0FU4MC68L11FC0PU3MC68L11FC0PU4
MC68HC11F1/FC0 MC68HC11FTS/DMOTOROLA
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TABLE OF CONTENTS
Section
Page
1
1.11.21.3
Introduction
1
Features ......................................................................................................................................1Ordering Information ...................................................................................................................2 Block Diagrams ..........................................................................................................................6
2
2.12.22.3
3
3.13.2
4
4.14.24.3
5
5.15.2
6
6.16.26.36.4
7
7.17.27.37.47.57.67.77.8
8
8.18.2
9
9.19.2
10
10.110.2
11
11.111.211.3
12
12.112.2
8
MC68HC11F1 Pin Assignments ..................................................................................................8MC68HC11FC0 Pin Assignments .............................................................................................10Pin Descriptions ........................................................................................................................12Control Registers14MC68HC11F1 Control Registers ...............................................................................................14MC68HC11FC0 Control Registers ............................................................................................16Operating Modes and System Initialization18Operating Modes .......................................................................................................................18Memory Maps ............................................................................................................................19System Initialization Registers ..................................................................................................20Resets and Interrupts25Interrupt Sources .......................................................................................................................25Reset and Interrupt Registers ...................................................................................................26Electrically Erasable Programmable ROM29EEPROM Operation ..................................................................................................................29EEPROM Registers ...................................................................................................................29EEPROM Programming and Erasure ........................................................................................31CONFIG Register Programming ...............................................................................................32Parallel Input/Output33Port A ........................................................................................................................................33Port B ........................................................................................................................................33Port C ........................................................................................................................................33Port D ........................................................................................................................................33Port E ........................................................................................................................................33Port F .........................................................................................................................................33Port G ........................................................................................................................................34Parallel I/O Registers ................................................................................................................34Chip-Selects38Chip-Select Operation ...............................................................................................................38Chip-Select Registers ................................................................................................................38Serial Communications Interface (SCI)42SCI Block Diagrams ..................................................................................................................42SCI Registers ............................................................................................................................44Serial Peripheral Interface49SPI Block Diagram ....................................................................................................................49SPI Registers ............................................................................................................................50Analog-to-Digital Converter53Input Pins ..................................................................................................................................54Conversion Sequence ...............................................................................................................54A/D Registers ............................................................................................................................55Main Timer57Timer Operation ........................................................................................................................57Timer Registers .........................................................................................................................59
Pulse Accumulator Block Diagram ............................................................................................Pulse Accumulator Registers ....................................................................................................
Pin Assignments and Signal Descriptions
13
13.113.2
Pulse Accumulator
MOTOROLA4MC68HC11F1/FC0MC68HC11FTS/D
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REGISTER INDEX
Register
AddressPage
ADCTL................A/D Control/Status.........................................................$1030 ..........................55BAUD..................Baud Rate......................................................................$102B ..........................44BPROT................Block Protect..................................................................$1035 ..........................29CFORC...............Timer Force Compare....................................................$100B ..........................59CONFIG..............EEPROM Mapping, COP, EEPROM Enables...............$103F .............24, 28, 30COPRST.............Arm/Reset COP Timer Circuitry.....................................$103A ..........................27CSCTL................Chip-Select Control........................................................$105D ..........................39CSGADR.............General-Purpose Chip-Select Address Register........... $105E .........................40CSGSIZ...............General-Purpose Chip-Select Size Register ................$105F ..........................40CSSTRH.............Clock Stretching.............................................................$105C ..........................38DDRA..................Port A Data Register......................................................$1001 ..........................34DDRC..................Data Direction Register for Port C.................................$1007 ..........................35DDRD..................Data Direction Register for Port D.................................$1009 ..........................36DDRG..................Data Direction Register for Port G.................................$1003 ..........................35HPRIO.................Highest Priority Interrupt and Miscellaneous ................$103C ...................20, 27INIT.....................RAM and I/O Mapping...................................................$103D ...................21, 22OC1D..................Output Compare 1 Data ................................................$100D ..........................59OC1M..................Output Compare 1 Mask ...............................................$100C ..........................59OPT2...................System Configuration Option Register 2.......................$1038 .............22, 36, 52OPTION..............System Configuration Options.......................................$1039 .............23, 26, 56PACNT................Pulse Accumulator Count..............................................$1027 ..........................66PACTL.................Pulse Accumulator Control ...........................................$1026 ...................63, 65PORTA................Port A Data....................................................................$1000 ..........................34PORTB................Port B Data....................................................................$1004 ..........................35PORTC................Port C Data....................................................................$1006 ..........................35PORTD................Port D Data....................................................................$1008 ..........................36PORTE................Port E Data....................................................................$100A ..........................36PORTF................Port F Data....................................................................$1005 ..........................35PORTG...............Port G Data....................................................................$1002 ..........................34PPROG...............EEPROM Programming Control....................................$103B ..........................30SCCR1................SCI Control 1 ................................................................$102C ..........................46SCCR2................SCI Control 2 ................................................................$102D ..........................46SCDR..................Serial Communications Data Register...........................$102F ..........................48SCSR..................SCI Status......................................................................$102E ..........................47SPCR..................Serial Peripheral Control ...............................................$1028 ..........................50SPDR..................SPI Data .......................................................................$102A ..........................51SPSR..................Serial Peripheral Status.................................................$1029 ..........................51TCNT...................Timer Count ..................................................................$100E, $100F ..............59TCTL1.................Timer Control 1..............................................................$1020 ..........................60TCTL2.................Timer Control 2..............................................................$1021 ..........................61TEST1.................Factory Test ..................................................................$103E ..........................24TFLG1.................Timer Interrupt Flag 1 ...................................................$1023 ..........................61TFLG2.................Timer Interrupt Flag 2 ...................................................$1025 ...................62, 65TI4O5..................Timer Input Capture 4/Output Compare 5 ....................$101E, $101F ..............60TIC1–TIC3...........Timer Input Capture ......................................................$1010–$1015 ..............60TMSK1................Timer Interrupt Mask 1 ..................................................$1022 ..........................61TMSK2................Timer Interrupt Mask 2 ..................................................$1024 ...................62, TOC1–TOC4.......Timer Output Compare .................................................$1016–$101D ..............60
MC68HC11F1/FC0 MC68HC11FTS/DMOTOROLA
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1.3 Block Diagrams
MODA/LIRMODB/VSTBY
VDDVSS
E
4XOUTXTALEXTALIRQXIRQRESETOSCILLATORPOWERCLOCKLOGICPAI/0C1PORT ADDRAPULSEACCUMULATORTIMERSYSTEMINTERRUPTLOGICCOPMODECONTROLA/DCONVERTERAN7AN6AN5AN4AN3AN2AN1AN0CSPROGCSGENCSIO1CSIO2VRHVRLPE7PE6PE5PE4PE3PE2PE1PE0PG7PG6PG5PG4PG3PG2PG1PG0
PA7PA6PA5PA4PA3PA2PA1PA0
OC2/OC1OC3/OC1OC4/OC1IC4/OC5/OC1IC3IC2IC1PERIODIC INTERRUPT512 BYTES EEPROM
PORT GPORT EDDRGPORT D1024 BYTES STATIC RAM
CHIPSELECTSCPUCORESCIRxDTxDPD0PD1
ADDRESS BUSADDR15ADDR14ADDR13ADDR12ADDR11ADDR10ADDR9ADDR8ADDR7ADDR6ADDR5ADDR4ADDR3ADDR2ADDR1ADDR0DATA BUSDATA7DATA6DATA5DATA4DATA3DATA2DATA1DATA0DDRDMISOMOSISCKSSSPIPD2
PD3PD4PD5
PORT BPORT FPORT CDDRCFigure 1 MC68HC11F1 Block Diagram
MOTOROLA6
PF0PF1PF2PF3PF4PF5PF6PF7PC0PC1PC2PC3PC4PC5PC6PC7PB7PB6PB5PB4PB3PB2PB1PB0R/WMC68HC11F1/FC0MC68HC11FTS/D
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VDDVSS
DSE4XOUTXTALEXTALIRQXIRQRESETMODA /LIRMODB /VSTBY
OSCILLATORPOWERCLOCKLOGICPAI/0C1PORT ADDRAPULSEACCUMULATORTIMERSYSTEMINTERRUPTLOGICCOPMODECONTROLPA7PA6PA5PA4PA3PA2PA1PA0
OC2/OC1OC3/OC1OC4/OC1IC4/OC5/OC1IC3IC2IC1PORT GPERIODIC INTERRUPT1024 BYTES STATIC RAM
CHIPSELECTSSCIRxDTxDPORT DDDRGWAITCSPROGCSGENCSIO1CSIO2PG7PG6PG5PG4PG3PG2PG1PG0
PD0PD1
PE6PE5PE4PE3PE2PE1
DDRDCPUCOREMISOMOSISCKSSSPIPD2
PD3PD4PD5
PORT EADDRESS BUSADDR15ADDR14ADDR13ADDR12ADDR11ADDR10ADDR9ADDR8ADDR7ADDR6ADDR5ADDR4ADDR3ADDR2ADDR1ADDR0DATA BUSDATA7DATA6DATA5DATA4DATA3DATA2DATA1DATA0PORT CDDRCPC0PC1PC2PC3PC4PC5PC6PC7R/WPORT BPORT FPB7PB6PB5PB4PB3PB2PB1PB0Figure 2 MC68HC11FC0 Block Diagram
MC68HC11F1/FC0 MC68HC11FTS/D
PF0PF1PF2PF3PF4PF5PF6PF7MOTOROLA
7
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2 Pin Assignments and Signal Descriptions
2.1 MC68HC11F1 Pin Assignments
MODB/VSTBYMODA/LIRPC0/DATA0PE7/AN7PE3/AN3PE6/AN6PE2/AN298765432PE5/AN5624XOUTEXTALXTALR/WVRHVSSVRLE68676665PC1/DATA1PC2/DATA2PC3/DATA3PC4/DATA4PC5/DATA5PC6/DATA6PC7/DATA7
RESETXIRQIRQPG7/CSPROGPG6/CSGENPG5/CSIO1PG4/CSIO2
PG3PG2PG1
11121314151617181920212223242526PB7/ADDR15 43272835363738394029303132333441PA0/IC342110636160595857565554PE1/AN1PE4/AN4PE0/AN0PF0/ADDR0PF1/ADDR1PF2/ADDR2PF3/ADDR3PF4/ADDR4PF5/ADDR5PF6/ADDR6PF7/ADDR7PB0/ADDR8PB1/ADDR9PB2/ADDR10PB3/ADDR11PB4/ADDR12PB5/ADDR13PB6/ADDR14
MC68HC11F1535251504948474544PA2/IC1PD0/RxDPD1/TxDPA7/PAI/OC1PD2/MISOPD3/MOSIPD4/SCKFigure 3 MC68HC11F1 68-Pin PLCC Pin Assignments
MOTOROLA8
PA3/OC5/IC4/OC1PA6/OC2/OC1PA5/OC3/OC1PA4/OC4/OC1PA1/IC2PG0PD5/SSVDDMC68HC11F1/FC0MC68HC11FTS/D
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PA3/OC5/IC4/OC1PA4/OC4/OC1PA5/OC3/OC1PA6/OC2/OC1PA7/PAI/OC1PB7/ADDR15PD3/MOSIPD2/MISOPD0/RXDPD4/SCKPD1/TXDPA0/IC3PA1/IC2PA2/IC1PD5/SSPG062VDDNCNC8079787776757473727170696867666563NCNC
PB6/ADDR14PB5/ADDR13PB4/ADDR12PB3/ADDR11PB2/ADDR10PB1/ADDR9PB0/ADDR8PF7/ADDR7PF6/ADDR6PF5/ADDR5PF4/ADDR4PF3/ADDR3PF2/ADDR2PF1/ADDR1PF0/ADDR0PE0/AN0PE4/AN4
NC
12345671011121314151617181920
343637212627282930313233353822232425394061605958575655545352
NCNCPG1PG2PG3PG4/CSIO2PG5/CSIO1PG6/CSGENPG7/CSPROGIRQXIRQRESETPC7/DATA7PC6/DATA6PC5/DATA5PC4/DATA4PC3/DATA3PC2/DATA2PC1/DATA1NCNC
MC68HC11F1
51504948474544434241
ENCNCVRLR/WVSSPE1/AN1PE5/AN5PE6/AN6PE3/AN3PE7/AN7EXTALXTALVRHNCPE2AN2MODA/LIR4XOUTFigure 4 Pin Assignments for the MC68HC11F1 80-Pin QFP
MC68HC11F1/FC0 MC68HC11FTS/D
MODB/VSTBYPC0/DATA0MOTOROLA
9
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2.2 MC68HC11FC0 Pin Assignments
PA3/IC4/OC5/OC1PA4/OC4/OC1PA5/OC3/OC1PA6/OC2/OC1PA7/PAI/OC1PB7/ADDR15PD3/MOSIPD2/MISO51PD4/SCK6261605958575655545352635049PD0/RxDPD1/TxDPA0/IC3PA1/IC2PA2/IC1PD5/SSVDDPB6/ADDR14PB5/ADDR13PB4/ADDR12PB3/ADDR11PB2/ADDR10PB1/ADDR9PB0/ADDR8PF7/ADDR7PF6/ADDR6PF5/ADDR5PF4/ADDR4PF3/ADDR3PF2/ADDR2PF1/ADDR1PF0/ADDR0
VSS
123456710111213141516
17181920212223242526272829303132484745444342
PG2PG3PG4/CSIO2PG5/CSIO1PG6/CSGENPG7/CSPROGIRQXIRQRESETPC7/DATA7PC6/DATA6PC5/DATA5PC4/DATA4PC3/DATA3PC2/DATA2PC1/DATA1
MC68HC11FC0
414039383736353433
VDDVSSPE1PE5PE2PE6PE3DSEWAITR/WMODA/LIREXTALXTALFigure 5 MC68HC11FC0 -Pin QFP Pin Assignments
MOTOROLA10
MODB/VSTBYPC0/DATA0MC68HC11F1/FC0MC68HC11FTS/D
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PA3/IC4/OC5/OC1PA4/OC4/OC1PA5/OC3/OC1PA6/OC2/OC1PA7/PAI/OC1PB7/ADDR15PD3/MOSIPD2/MISOPD4/SCKPD0/RXD63PD1/TXDPA0/IC3PA1/IC2PA2/IC1VDDPD5/SSPG062NC807977767574737271706968676665NCNC
PB6/ADDR14PB5/ADDR13PB4/ADDR12PB3/ADDR11PB2/ADDR10PB1/ADDR9PB0/ADDR8PF7/ADDR7PF6/ADDR6PF5/ADDR5PF4/ADDR4PF3/ADDR3PF2/ADDR2PF1/ADDR1PF0/ADDR0
VSSPE4NC
12345671011121314151617181920
21222324252627282930313233343536373839407861605958575655545352
NCNCPG1PG2PG3PG4/CSIO0PG5/CSIO1PG6/CSGENPG7/CSPROGIRQXIRQRESETPC7/DATA7PC6/DATA6PC5/DATA5PC4/DATA4PC3/DATA3PC2/DATA2PC1/DATA1NCNC
MC68HC11FC0
51504948474544434241
VSSVDDPE1PE5PE2PE6PE3DSENCNCWAITR/WEXTALXTALNCMODA/LIR4XOUTFigure 6 MC68HC11FC0 80-Pin TQFP Pin Assignments
MC68HC11F1/FC0 MC68HC11FTS/D
MODB/VSTBYPC0/DATA0MOTOROLA
11
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2.3 Pin Descriptions
VDD and VSS
VDD is the positive power input to the MCU, and VSS is ground.
RESETThis active-low input initializes the MCU to a known startup state. It also acts as an open-drainoutput to indicate that an internal failure has been detected in either the clock monitor or the COPwatchdog circuits.XTAL and EXTAL
These two pins provide the interface for either a crystal or a CMOS-compatible clock to drive theinternal clock circuitry. The frequency applied to these pins is four times the desired busfrequency (E clock).E
This pin provides an output for the E clock, the basic timing reference signal for the bus circuitry.The address bus is active when E is low, and the data bus is active when E is high.DSThe data strobe output is the inverted E clock. DS is present on the MC68HC11FC0 only.WAIT
This input is used to stretch the bus cycle to accomodate slower devices. The MCU samples thelogic level at this pin on the rising edge of E clock. If it is high, the MCU holds the E clock high forthe next four EXTAL clock cycles. If it is low, the E clock responds normally, going low twoEXTAL cycles later. The WAIT pin is present on the MC68HC11FC0 only.4XOUT
This pin provides a buffered oscillator signal to drive another M68HC11 MCU. The 4XOUT pin isnot present on the -pin QFP MC68HC11FC0 package.IRQThis active-low input provides a means of generating asynchronous, maskable interrupt requestsfor the CPU.
XIRQThis interrupt request input can be made non-maskable by clearing the X bit in the MCU’scondition code register.MODA/LIR and MODB/VSTBYThe logic level applied to the MODA and MODB pins at reset determines the MCU’s opreatingmode (see Table 7 in 4 Operating Modes and System Initialization). After reset, MODAfunctions as LIR, an open-drain output that indicates the start of an instruction cycle. MODBfunctions as VSTBY, providing a backup battery to maintain the contents of RAM when VDD falls.R/WIn expanded and test modes, R/W indicates the direction of transfers on the external data bus.VRH and VRL
These pins provide the reference voltage for the analog-to-digital converter. Use bypasscapacitors to minimize noise on these signals. Any noise on VRH and VRL will directly affect A/Daccuracy. These pins are not present on the MC68HC11FC0.
MOTOROLA12MC68HC11F1/FC0MC68HC11FTS/D
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Port Signals
On the MC68HC11F1, 54 pins are arranged into six 8-bit ports (ports A, B, C, E, F, and G) andone 6-bit port (port D). On the MC68HC11FC0, either 52 or 49 pins are available, depending onthe package. General-purpose I/O port signals are discussed briefly in the following pragraphs.For additional information, refer to 7 Parallel Input/Output.Port A Pins
Port A is an 8-bit general-purpose I/O port (PA[7:0]) with a data register (PORTA) and a datadirection register (DDRA). Port A pins share functions with the 16-bit timer system. Out of reset,PA[7:0] are general-purpose high-impedance inputs.Port B Pins
Port B is an 8-bit output-only port. In single-chip modes, port B pins are general-purpose outputpins (PB[7:0]). In expanded modes, port B pins act as the high-order address lines ADDR[15:8].Port C Pins
Port C is an 8-bit general-purpose I/O port with a data register (PORTC) and a data directionregister (DDRC). In single-chip modes, port C pins are general-purpose I/O pins PC[7:0]. Inexpanded modes, port C pins are configured as data bus pins DATA[7:0].Port D Pins
Port D is a 6-bit general-purpose I/O port with a data register (PORTD) and a data directionregister (DDRD). The six port D lines PD[5:0] can be used for general-purpose I/O or for the serialcommunications interface (SCI) or serial peripheral interface (SPI) subsystems.Port E Pins
Port E is an 8-bit input-only port that is also used as the analog input port for the analog-to-digitalconverter. Port E pins that are not used for the A/D system can be used as general-purposeinputs. However, PORTE should not be read during the sample portion of an A/D conversionsequence.
NOTE
The A/D system is not available on the MC68HC11FC0. PE7 and PE0 are notavailable on the 80-pin MC68HC11FC0. PE7, PE4, and PE0 are not available onthe -pin MC68HC11FC0.
Port F Pins
Port F is an 8-bit output-only port. In single-chip mode, port F pins are general-purpose outputpins PF[7:0]. In expanded mode, port F pins act as the low-order address outputs ADDR[7:0].Port G Pins
Port G is an 8-bit general-purpose I/O port. When enabled, four chip select signals are alternatefunctions of PG[7:4].
NOTE
PG[1:0] are not available on the -pin MC68HC11FC0.
MC68HC11F1/FC0 MC68HC11FTS/DMOTOROLA
13
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3 Control Registers
The MC68HC11F1 and MC68HC11FC0 control registers determine most of the system’s operatingcharacteristics. They occupy a 96-byte relocatable memory block. Their names and bit mnemonics aresummarized in the following table. Addresses shown are the default locations out of reset.3.1 MC68HC11F1 Control Registers
Table 5 MC68HC11F1 Register and Control Bit Assignments
$1000$1001$1002$1003$1004$1005$1006$1007$1008$1009$100A$100B$100C$100D$100E$100F$1010$1011$1012$1013$1014$1015$1016$1017$1018$1019$101A$101B$101C$101D$101E$101F$1020$1021
Bit 7PA7DDA7PG7DDG7PB7PF7PC7DDC700PE7FOC1OC1M7OC1D7Bit 15Bit 7Bit 15Bit 7Bit 15Bit 7Bit 15Bit 7Bit 15Bit 7Bit 15Bit 7Bit 15Bit 7Bit 15Bit 7Bit 15Bit 7OM2EDG4B6PA6DDA6PG6DDG6PB6PF6PC6DDC600PE6FOC2OC1M6OC1D6146146146146146146146146146OL2EDG4A5PA5DDA5PG5DDG5PB5PF5PC5DDC5PD5DDD5PE5FOC3OC1M5OC1D5135135135135135135135135135OM3EDG1B4PA4DDA4PG4DDG4PB4PF4PC4DDC4PD4DDD4PE4FOC4OC1M4OC1D4124124124124124124124124124OL3EDG1A3PA3DDA3PG3DDG3PB3PF3PC3DDC3PD3DDD3PE3FOC5OC1M3OC1D3113113113113113113113113113OM4EDG2B2PA2DDA2PG2DDG2PB2PF2PC2DDC2PD2DDD2PE2000102102102102102102102102102OL4EDG2A1PA1DDA1PG1DDG1PB1PF1PC1DDC1PD1DDD1PE1000919191919191919191OM5EDG3BBit 0PA0DDA0PG0DDG0PB0PF0PC0DDC0PD0DDD0PE0000Bit 8Bit 0Bit 8Bit 0Bit 8Bit 0Bit 8Bit 0Bit 8Bit 0Bit 8Bit 0Bit 8Bit 0Bit 8Bit 0Bit 8Bit 0OL5EDG3APORTADDRAPORTGDDRGPORTBPORTFPORTCDDRCPORTDDDRDPORTECFORCOC1MOC1DTCNT (High)TCNT (Low)TIC1 (High)TIC1 (Low)TIC2 (High)TIC2 (Low)TIC3 (High)TIC3 (Low)TOC1 (High)TOC1 (Low)TOC2 (High)TOC2 (Low)TOC3 (High)TOC3 (Low)TOC4 (High)TOC4 (Low)TI4/O5 (High)TI4/O5 (Low)TCTL1TCTL2
MOTOROLA14MC68HC11F1/FC0MC68HC11FTS/D
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Table 5 MC68HC11F1 Register and Control Bit Assignments (Continued)
Bit 7
$1022$1023$1024$1025$1026$1027$1028$1029$102A$102B$102C$102D$102E$102F$1030$1031$1032$1033$1034$1035$1036$1037$1038$1039$103A$103B$103C$103D$103E$103F$1040to$105B$105C$105D$105E$105F
I01SAI01ENGA15I01AVI01SBI01PLGA14I02AVI02SAI02ENGA130I02SBI02PLGA12GNPOLGSTHAGCSPRGA11GAVLDGSTGBPCSENGA10GSIZAPSTHAPSIZA0GSIZBPSTHBPSIZB0GSIZCGWOM0Bit 7ODDRBOOTRAM3TILOPEE3
CWOM06EVENSMODRAM20EE2
CLK4XIRQE50MDARAM1OCCREE1
LIRDVDLY4BYTEIRVRAM0CBYPEE0
0CME3ROWPSEL3REG3DISR1
SPRBYPFCME2ERASEPSEL2REG2FCMNOCOP
0CR11EELATPSEL1REG1FCOP1
0CR0Bit 0EEPGMPSEL0REG00EEON
OC1IOC1FTOITOF0Bit 7SPIESPIFBit 7TCLRR8TIETDREBit 7CCFBit 7Bit 7Bit 7Bit 70
6OC2IOC2FRTIIRTIFPAEN6SPEWCOL6SCP2T8TCIETC6066660
5OC3IOC3FPAOVIPAOVFPAMOD5DWOM05SCP10RIERDRF5SCAN55550
4OC4IOC4FPAIIPAIFPEDGE4MSTRMODF4SCP0MILIEIDLE4MULT4444PTCON
3I4/O5II4/O5F0003CPOL03RCKBWAKETEOR3CD3333BPRT3
2IC1IIC1F00I4/052CPHA02SCR20RENF2CC2222BPRT2
1IC2IIC2FPR10RTR11SPR101SCR10RWUFE1CB1111BPRT1
Bit 0IC3IIC3FPR00RTR0Bit 0SPR00Bit 0SCR00SBK0Bit 0CABit 0Bit 0Bit 0Bit 0BPRT0
TMSK1TFLG1TMSK2TFLG2PACTLPACNTSPCRSPSRSPDRBAUDSCCR1SCCR2SCSRSCDRADCTLADR1ADR2ADR3ADR4BPROTReservedReservedOPT2OPTION COPRSTPPROG HPRIO INITTEST1CONFIG ReservedReservedCSSTRHCSCTLCSGADRCSGSIZ
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3.2 MC68HC11FC0 Control Registers
Table 6 MC68HC11FC0 Register and Control Bit Assignments
$1000$1001$1002$1003$1004$1005$1006$1007$1008$1009$100A$100B$100C$100D$100E$100F$1010$1011$1012$1013$1014$1015$1016$1017$1018$1019$101A$101B$101C$101D$101E$101F$1020$1021$1022$1023$1024$1025
Bit 7PA7DDA7PG7DDG7PB7PF7PC7DDC700PE7FOC1OC1M7OC1D7Bit 15Bit 7Bit 15Bit 7Bit 15Bit 7Bit 15Bit 7Bit 15Bit 7Bit 15Bit 7Bit 15Bit 7Bit 15Bit 7Bit 15Bit 7OM2EDG4BOC1IOC1FTOITOF6PA6DDA6PG6DDG6PB6PF6PC6DDC600PE6FOC2OC1M6OC1D6146146146146146146146146146OL2EDG4AOC2IOC2FRTIIRTIF5PA5DDA5PG5DDG5PB5PF5PC5DDC5PD5DDD5PE5FOC3OC1M5OC1D5135135135135135135135135135OM3EDG1BOC3IOC3FPAOVIPAOVF4PA4DDA4PG4DDG4PB4PF4PC4DDC4PD4DDD4PE4FOC4OC1M4OC1D4124124124124124124124124124OL3EDG1AOC4IOC4FPAIIPAIF3PA3DDA3PG3DDG3PB3PF3PC3DDC3PD3DDD3PE3FOC5OC1M3OC1D3113113113113113113113113113OM4EDG2BI4/O5II4/O5F002PA2DDA2PG2DDG2PB2PF2PC2DDC2PD2DDD2PE2000102102102102102102102102102OL4EDG2AIC1IIC1F001PA1DDA1PG1DDG1PB1PF1PC1DDC1PD1DDD1PE1000919191919191919191OM5EDG3BIC2IIC2FPR10Bit 0PA0DDA0PG0DDG0PB0PF0PC0DDC0PD0DDD0PE0000Bit 8Bit 0Bit 8Bit 0Bit 8Bit 0Bit 8Bit 0Bit 8Bit 0Bit 8Bit 0Bit 8Bit 0Bit 8Bit 0Bit 8Bit 0OL5EDG3AIC3IIC3FPR00PORTADDRAPORTGDDRGPORTBPORTFPORTCDDRCPORTDDDRDPORTECFORCOC1MOC1DTCNT (High)TCNT (Low)TIC1 (High)TIC1 (Low)TIC2 (High)TIC2 (Low)TIC3 (High)TIC3 (Low)TOC1 (High)TOC1 (Low)TOC2 (High)TOC2 (Low)TOC3 (High)TOC3 (Low)TOC4 (High)TOC4 (Low)TI4/O5 (High)TI4/O5 (Low)TCTL1TCTL2TMSK1TFLG1TMSK2TFLG2
MOTOROLA16MC68HC11F1/FC0MC68HC11FTS/D
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Table 6 MC68HC11FC0 Register and Control Bit Assignments (Continued)
Bit 7
$1026$1027$1028$1029$102A$102B$102C$102D$102E$102F$1030to$1037$1038$1039$103A$103B$103C$103D$103E$103F$1040to$105B$105C$105D$105E$105F
I01SAI01ENGA15I01AVI01SBI01PLGA14I02AVI02SAI02ENGA130I02SBI02PLGA12GNPOLGSTHAGCSPRGA11GAVLDGSTGBPCSENGA10GSIZAPSTHAPSIZA0GSIZBPSTHBPSIZB0GSIZCRBOOTRAM5TILOP0SMODRAM400MDARAM3OCCR0IRVRAM2CBYP0PSEL3RAM1DISR0PSEL2RAM0FCMNOCOPPSEL1REG1FCOP0PSEL0REG000GWOM0Bit 7CWOM06CLK4XIRQE5LIRDVDLY40CME3SPRBYPFCME20CR110CR0Bit 00Bit 7SPIESPIFBit 7TCLRR8TIETDREBit 76PAEN6SPEWCOL6SCP2T8TCIETC65PAMOD5DWOM05SCP10RIERDRF54PEDGE4MSTRMODF4SCP0MILIEIDLE4303CPOL03RCKBWAKETEOR32I4/052CPHA02SCR20RENF21RTR11SPR101SCR10RWUFE1Bit 0RTR0Bit 0SPR00Bit 0SCR00SBK0Bit 0PACTLPACNTSPCRSPSRSPDRBAUDSCCR1SCCR2SCSRSCDRReservedReservedOPT2OPTION COPRSTReserved HPRIO INITTEST1CONFIG ReservedReservedCSSTRHCSCTLCSGADRCSGSIZ
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4 Operating Modes and System Initialization
The 16-bit address bus can access Kbytes of memory. Because the MC68HC11F1 andMC68HC11FC0 are intended to operate principally in expanded mode, there is no internal ROM andthe address bus is non-multiplexed. Both devices include 1 Kbyte of static RAM, a 96-byte control reg-ister block, and 256 bytes of bootstrap ROM. The MC68HC11F1 also includes 512 bytes of EEPROM.RAM and registers can be remapped on both the MC68HC11F1 and the MC68HC11FC0. On both theMC68HC11F1 and the MC68HC11FC0, out of reset RAM resides at $0000 to $03FF and registers re-side at $1000 to $105F. On the MC68HC11F1, RAM and registers can both be remapped to any 4-Kbyte boundary. On the MC68HC11FC0, RAM can be remapped to any 1-Kbyte boundary, and regis-ters can be remapped to any 4-Kbyte boundary in the first 16 Kbytes of address space.
RAM and control register locations are defined by the INIT register, which can be written only once with-in the first E-clock cycles after a reset in normal modes. It becomes a read-only register thereafter.If RAM and the control register block are mapped to the same boundary, the register block has priorityof the first 96 bytes.
In expanded and special test modes in the MC68HC11F1, EEPROM is located from $xE00 to $xFFF,where x represents the value of the four high-order bits of the CONFIG register. EEPROM is enabledby the EEON bit of the CONFIG register. In single-chip and bootstrap modes, the EEPROM is locatedfrom $FE00 to $FFFF.4.1 Operating Modes
Bootstrap ROM resides at addresses $BF00–$BFFF, and is only available when the MCU operates inspecial bootstrap operating mode. Operating modes are determined by the logic levels applied to theMODB and MODA pins at reset.
In single-chip mode, the MCU functions as a self-contained microcontroller and has no external addressor data bus. Ports B, C and F are available for general-purpose I/O (GPIO). Ports B and F are outputsonly; each of the port C pins can be configured as input or output.
CAUTION
The MC68HC11FC0 must not be configured to boot in single-chip mode becauseit has no internal ROM or EEPROM. Operation of the device in single-chip modewill result in erratic behavior.
In expanded mode, the MCU can access external memory. Ports B and F provide the address bus, andport C is the data bus.
Special bootstrap mode is a variation of single chip mode that provides access to the internal bootstrapROM. In this mode, the user can download a program into on-chip RAM through the serial communica-tion interface (SCI).
Special test mode, a variation of expanded mode, is primarily used during Motorola’s internal productiontesting, but can support emulation and debugging during program development.
Table 7 shows a summary of operating modes, mode select pins, and control bits in the HPRIO register.
Table 7 Hardware Mode Select Summary
Input PinsMODBMODA10110001
Mode DescriptionSingle Chip
Expanded
Special BootstrapSpecial Test
Control Bits in HPRIO (Latched at Reset)RBOOTSMODMDA
000001110011
MOTOROLA
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4.2 Memory Maps
x000
1024 BYTES RAM1
$03FF —
—
EXTERNAL$1000 —$105F —
——
——
——
y05F
—
—
EXTERNALy000
96-BYTE REGISTER FILE2
x3FF$0000 ————
EXTERNALEXTERNAL$BFC0
$BF00 —
—
—
—
256 BYTESBOOTSTRAPROMSPECIALMODEINTERRUPTVECTORS3$BFFFRESERVED4$FE00 — $FFC0 —$FFFF —
SINGLECHIPMODA = 0MODB = 1
——
EXPANDED
——
SPECIALBOOTSTRAPMODA = 0MODB = 0
——
SPECIALTESTMODA = 1MODB = 0
512BYTESEEPROM5$FFC0NORMALMODEINTERRUPTVECTORS$FFFF$BFFF ————
MODA = 1MODB = 1
NOTES:
1. RAM can be remapped to any 4-Kbyte boundary ($x000). “x” represents the value contained in RAM[3:0] in theINIT register.
2. The register block can be remapped to any 4-Kbyte boundary ($y000). “y” represents the value contained inREG[3:0] in the INIT register.
3. Special test mode vectors are externally addressed.
4. In special test mode the address locations $zD00—$zDFF are not externally addressable. “z” represents the val-ue of bits EE[3:0] in the CONFIG register.
5. EEPROM can be remapped to any 4-Kbyte boundary ($z000). “z” represents the value contained in EE[3:0] inthe CONFIG register.
Figure 7 MC68HC11F1 Memory Map
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$0000 ————
1024 BYTES RAM1
$03FF ——
EXTERNAL——
EXTERNAL$1000 —$105F —
——
——
——
96-BYTE REGISTER FILE2
EXTERNALEXTERNAL$BFC0
$BF00 —
—
—
—
256 BYTESBOOTSTRAPROMSPECIALMODEINTERRUPTVECTORS$BFFF$FFC0
$FE00 — $FFC0 —$FFFF —
SINGLECHIPMODA = 0MODB = 1
——
EXPANDED
——
SPECIALBOOTSTRAPMODA = 0MODB = 0
——
SPECIALTESTMODA = 1MODB = 0
NORMALMODEINTERRUPTVECTORS$FFFF$BFFF ————
MODA = 1MODB = 1
NOTES:
1. RAM can be remapped to any 1-Kbyte boundary, depending on the value contained in the RAM field in the INITregister.
2. The register block can be remapped to $0000, $2000, or $3000, depending on the value contained in REG[1:0]in the INIT register.
Figure 8 MC68HC11FC0 Memory Map
4.3 System Initialization Registers
HPRIO — Highest Priority Interrupt and Miscellaneous
Bit 7RBOOTRESET:0 0106SMOD0 0115MDA01014IRV00113PSEL300002PSEL211111PSEL10000Bit 0PSEL01111Single-ChipExpandedBootstrapSpecial Test$x03C
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RBOOT — Read Bootstrap ROM
RBOOT is valid only when SMOD is set to one (special bootstrap or special test mode). RBOOT canonly be written in special modes but can be read anytime.
0 = Boot loader ROM disabled and not in memory map
1 = Boot loader ROM enabled and in memory map at $BF00–$BFFFSMOD and MDA — Special Mode Select and Mode Select A
The initial value of SMOD is the inverse of the logic level present on the MODB pin at the rising edgeof reset. The initial value of MDA equals the logic level present on the MODA pin at the rising edge ofreset. These two bits can be read at any time. They can be written at any time in special modes. Neitherbit can be written in normal modes. SMOD cannot be set once it has been cleared. Refer to Table 8.
Table 8 Hardware Mode Select Summary
Input PinsMODB1100
MODA0101
Mode DescriptionSingle ChipExpandedSpecial BootstrapSpecial Test
Control Bits in HPRIO (Latched at Reset)RBOOT
0010
SMOD0011
MDA0101
IRV — Internal Read Visibility
This bit can be read at any time. It can be written at any time in special modes, but only once in normalmodes. In single-chip and bootstrap modes, IRV has no meaning or effect.
0 = Internal reads not visible
1 = Data from internal reads is driven on the external data busPSEL[3:0] — See 5.2 Reset and Interrupt Registers, page 27.INIT — RAM and I/O Mapping (MC68HC11FC0 only)
Bit 7RAM5RESET:06RAM405RAM304RAM203RAM102RAM001REG10Bit 0REG01$x03D
The INIT register can be written only once in first cycles out of reset in normal modes, or at any timein special modes.
NOTE
The register diagram above applies to the MC68HC11FC0 only. A diagram and bitdescriptions of the INIT register in the MC68HC11F1 are provided elsewhere inthis section.
RAM[5:0] — Internal RAM Map Position
These bits determine the upper six bits of the RAM address and allow mapping of the RAM to any one-Kbyte boundary.REG[1:0] — Register Block Map Position
These bits determine the location of the register block, as shown in Table 9.
Table 9 Register Block Location
REG[1:0]0 00 11 01 1
Register Block Address
$0000 – $005F$1000 – $105F$2000 – $205F$3000 – $305F
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INIT — RAM and I/O Mapping (MC68HC11F1 only)
Bit 7RAM3RESET:06RAM205RAM104RAM003REG302REG401REG10Bit 0REG01$x03D
The INIT register can be written only once in first cycles out of reset in normal modes, or at any timein special modes.
NOTE
The register diagram above applies to the MC68HC11F1 only. A diagram and bitdescriptions of the INIT register in the MC68HC11FC0 are provided elsewhere inthis section.
RAM[3:0] — Internal RAM Map Position
These bits determine the upper four bits of the RAM address and allow mapping of the RAM to any four-Kbyte boundary. Refer to Table 10.REG[3:0] — 96-Byte Register Block Map Position
These bits determine bits the upper 4 bits of the register block and allow mapping of the register blockto any four-Kbyte boundary. Refer to Table 10.
Table 10 RAM and Register Mapping
RAM[3:0]0000000100100011010001010110011110001001101010111100110111101111
Location$0000-$03FF$1000-$13FF$2000-$23FF$3000-$33FF$4000-$43FF$5000-$53FF$6000-$63FF$7000-$73FF$8000-$83FF$9000-$93FF$A000-$A3FF$B000-$B3FF$C000-$C3FF$D000-$D3FF$E000-$E3FF$F000-$F3FF
REG[3:0]0000000100100011010001010110011110001001101010111100110111101111
Location$0000-$005F$1000-$105F$2000-$205F$3000-$305F$4000-$405F$5000-$505F$6000-$605F$7000-$705F$8000-$805F$9000-$905F$A000-$A05F$B000-$B05F$C000-$C05F$D000-$D05F$E000-$E05F$F000-$F05F
OPT2 — System Configuration Option Register 2
Bit 7GWOMRESET06CWOM05CLK4X14LIRDV03—02SPRBYP01—0Bit 0—0$x038
GWOM — Port G Wired-OR Mode Option
Refer to 7.8 Parallel I/O Registers, page 36.
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CWOM — Port C Wired-OR Mode Option
Refer to 7.8 Parallel I/O Registers, page 37.
CLK4X — 4XCLK Output Enable
This bit can only be written once after reset in all modes.
0 = 4XOUT clock output is disabled
1 = Buffered oscillator is driven on the 4XOUT clock output
LIRDV — Load Instruction Register Driven
In order to detect consecutive instructions in a high-speed application, LIR can be driven high for onequarter of an E-clock cycle during each instruction fetch.
0 = LIR signal is not driven high.1 = LIR signal is driven high.Bits 3, 1, 0 — Not implemented. Reads always return zero and writes have no effect.SPRBYP — See 10.2 SPI Registers, page 52.OPTION — System Configuration Options
Bit 7ADPURESET:06CSEL05IRQE*04DLY*13CME02FCME*01CR1*0Bit 0CR0*0$x039
*Can be written only once in first cycles out of reset in normal modes, or at any time in special modes.
ADPU — A/D Power-Up
This bit is implemented on the MC68HC11F1 only. On the MC68HC11FC0, reads always return zeroand writes have no effect.
0 = A/D system disabled1 = A/D system enabledCSEL — Clock Select
This bit is implemented on the MC68HC11F1 only. On the MC68HC11FC0, reads always return zeroand writes have no effect.
0 = A/D and EEPROM use system E clock1 = A/D and EEPROM use internal RC clockIRQE — IRQ Select Edge Sensitive Only0 = Low level recognition1 = Falling edge recognition
DLY — Enable Oscillator Start-Up Delay on Exit from STOP
0 = No stabilization delay on exit from STOP
1 = Stabilization delay of 40 E-clock cycles is enabled on exit from STOPCME — Clock Monitor Enable
0 = Clock monitor disabled; slow clocks can be used1 = Slow or stopped clocks cause clock failure resetFCME — Force Clock Monitor Enable
0 = Clock monitor circuit follows the state of the CME bit1 = Clock monitor circuit is enabled until the next reset
In order to use both STOP and the clock monitor, the CME bit should be written to zero prior to executinga STOP instruction and rewritten to one after recovery from STOP. FCME should be kept cleared if theuser intends to use the STOP instruction.
CR[1:0] — COP Timer Rate Select
Refer to 5.2 Reset and Interrupt Registers, page 27.
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CONFIG — EEPROM Mapping, COP, EEPROM Enables $x03F
Bit 7EE3
RESET
U
6EE2U
5EE1U
4EE0U
311
2NOCOPU
111
Bit 0EEONU
U = Unaffected by reset
Bits 7:3 — See 6.2 EEPROM Registers, page 30. (These bits are implemented on the MC68HC11F1 only.)NOCOP — COP System Disable
0 = COP enabled (forces reset on time-out)
1 = COP disabled (does not force reset on time-out)TEST1 — Factory Test
Bit 7TILOPRESET:06005OCCR04CBYP03DISR—2FCM01FCOP0Bit 000$x03E
These bits can only be written in test and bootstrap modes.
TILOP — Test Illegal Opcode
This test mode allows serial testing of all illegal opcodes without servicing an interrupt after each illegalopcode is fetched.
0 = Normal operation (trap on illegal opcodes)1 = Inhibit LIR when an illegal opcode is foundBit 6 — Not implemented. Reads always return zero and writes have no effect.
OCCR — Output Condition Code Register to Timer Port
0 = Normal operation
1 = Condition code bits H, N, Z, V and C are driven on PA[7:3] to allow a test system to monitor
CPU operationCBYP — Timer Divider Chain Bypass
0 = Normal operation
1 = The 16-bit free-running timer is divided into two 8-bit halves and the prescaler is bypassed. The
system E clock drives both halves directly.DISR — Disable Resets from COP and Clock Monitor
In test and bootstrap modes, this bit is reset to one to inhibit clock monitor and COP resets. In normalmodes, DISR is reset to zero.
0 = Normal operation
1 = COP and Clock Monitor failure do not generate a system resetFCM — Force Clock Monitor Failure
0 = Normal operation
1 = Generate an immediate clock monitor failure reset. Note that the CME bit in the OPTION register
must also be set in order to force the reset.FCOP — Force COP Watchdog Failure
0 = Normal operation
1 = Generate an immediate COP failure reset. Note that the NOCOP bit in the CONFIG register
must be cleared (COP enabled) in order to force the reset.Bit 0 — Not implemented. Reads always return zero and writes have no effect.
MOTOROLA24MC68HC11F1/FC0MC68HC11FTS/D
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5 Resets and Interrupts
There are three sources of reset on the MC68HC11F1 and MC68HC11FC0, each having its own resetvector:
• RESET pin• Clock monitor failure
• Computer operating properly (COP) failure
There are 22 interrupt sources serviced by 18 interrupt vectors. (The SCI interrupt vector services fiveSCI interrupt sources.) Three of the interrupt vectors are non-maskable:
• Illegal opcode trap• Software interrupt
• XIRQ pin (pseudo non-maskable interrupt)The other 19 interrupts, generated mostly by on-chip peripheral systems, are maskable. Maskable in-terrupts are recognized only if the global interrupt mask bit (I) in the condition code register (CCR) isclear. Maskable interrupts have a default priority arrangement out of reset. However, any one interruptsource can be elevated to the highest maskable priority position by writing to the HPRIO register. Thisregister can be written at any time, provided the I bit in the CCR is set.
In addition to the global I bit, all maskable interrupt sources except the external interrupt (IRQ pin) aresubject to local enable bits in control registers. Each of these interrupt sources also sets a correspond-ing flag bit in a control register that can be polled by software.
Several of these flags are automatically cleared during the normal course of responding to the interruptrequests. For example, the RDRF flag is set when a byte has been received in the SCI. The normalresponse to an RDRF interrupt request is to read the SCI status register to check for receive errors,then to read the received data from the SCI data register. It is precisely these two steps that are requiredto clear the RDRF flag, so no further instructions are necessary.5.1 Interrupt Sources
The following table summarizes the interrupt sources, vector addresses, masks, and flag bits.
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Table 11 Interrupt and Reset Vector Assignments
Vector Address
FFC0, C1
toFFD4, D5FFD6, D7
Interrupt Source
Reserved
SCI Serial SystemSCI Transmit Complete
SCI Transmit Data Register EmptySCI Idle Line DetectSCI Receiver Overrun
SCI Receive Data Register Full
FFD8, D9FFDA, DBFFDC, DDFFDE, DFFFE0, E1FFE2, E3FFE4, E5FFE6, E7FFE8, E9FFEA, EBFFEC, EDFFEE, EFFFF0, F1FFF2, F3FFF4, F5FFF6, F7FFF8, F9FFFA, FBFFFC, FDFFFE, FF
SPI Serial Transfer CompletePulse Accumulator Input EdgePulse Accumulator OverflowTimer Overflow
Timer Input Capture 4/Output Compare 5Timer Output Compare 4Timer Output Compare 3Timer Output Compare 2Timer Output Compare 1Timer Input Capture 3Timer Input Capture 2Timer Input Capture 1Real-Time InterruptXIRQ PinSoftware InterruptIllegal Opcode TrapCOP Failure Clock Monitor FailRESET
I BitI BitI BitI BitI BitI BitI BitI BitI BitI BitI BitI BitI BitX BitNoneNoneNoneNoneNoneI Bit
TCIETIEILIERIERIESPIEPAIIPAOVITOII4/O5IOC4IOC3IOC2IOC1IIC3IIC2IIC1IRTIINoneNoneNoneNOCOPCMENone
TCTDREIDLEORRDRFSPIFPAIFPAOVFTOFI4/O5FOC4FOC3FOC2FOC1FIC3FIC2FIC1FRTIFNoneNoneNoneNoneNoneNone
CCR Mask
—
Local Mask
—
Flag Bit—
BitNoneNoneIRQ I 5.2 Reset and Interrupt RegistersOPTION — System Configuration Options
Bit 7ADPURESET:06CSEL05IRQE*04DLY*13CME02FCME*01CR1*0Bit 0CR0*0$x039
*Can be written only once in first cycles out of reset in normal modes, or at any time in special modes.
Bits [7:6], [4:2]
Refer to 4.3 System Initialization Registers, page 23, and 11.3 A/D Registers, page 56.IRQE — IRQ Select Edge Sensitive Only0 = Low level recognition1 = Falling edge recognition
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CR[1:0] — COP Timer Rate Select
The COP system is driven by a constant frequency of E/215. CR[1:0] specify an additional divide-by fac-tor to arrive at the COP time-out rate.
Table 12 COP Watchdog Time-Out Periods
Frequency1 MHz2 MHz3 MHz4 MHz5 MHz6 MHzAny E
Tolerance-0/+32.768 ms-0/+16.384 ms-0/+10.923 ms-0/+8.192 ms-0/+6.554 ms-0/+5.461 ms-0/+215/E
CR[1:0] = 0032.768 ms16.384 ms10.923 ms8.192 ms6.554 ms5.461 ms215/E
CR[1:0] = 01131.072 ms65.536 ms43.691 ms32.768 ms26.214 ms21.845217/E
CR[1:0] = 10524.288 ms262.144 ms174.763 ms131.072 ms104.858 ms87.381 ms219/E
CR[1:0] = 112.097 s1.049 s699.051 ms524.288 ms419.430 ms349.525 ms221/E
COPRST — Arm/Reset COP Timer Circuitry
Bit 77RESET:066055044033 022 011 0Bit 00 0$x03A
Write $55 to COPRST to arm the COP watchdog clearing mechanism. Then write $AA to COPRST toreset the COP timer. Performing instructions between these two steps is possible provided both stepsare completed in the correct sequence before the timer times out.
HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous $x03C
Bit 7
RESET:
6
5MDA 4IRV
3PSEL30
2PSEL21
1PSEL10
Bit 0PSEL01
RBOOT SMODBits [7:4] — See 4.3 System Initialization Registers, page 20.
PSEL[3:0] — Interrupt Priority Select Bits
Can be written only while the I bit in the CCR is set (interrupts disabled). These bits select one interruptsource to have priority over other I-bit related sources.
Table 13 Highest Priority Interrupt Selection
PSEL[3:0]00000001001000110100010101100111100010011010
Interrupt Source Promoted
Timer Overflow
Pulse Accumulator OverflowPulse Accumulator Input EdgeSPI Serial Transfer CompleteSCI Serial SystemReserved (Default to IRQ)IRQ (External Pin)Real-Time InterruptTimer Input Capture 1Timer Input Capture 2Timer Input Capture 3
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Table 13 Highest Priority Interrupt Selection (Continued)
PSEL[3:0]10111100110111101111
Interrupt Source Promoted
Timer Output Compare 1Timer Output Compare 2Timer Output Compare 3Timer Output Compare 4
Timer Output Compare 5/Input Capture 4
CONFIG — EEPROM Mapping, COP, EEPROM Enables $x03F
Bit 7EE3RESETU6EE2U5EE1U4EE0U3112NOCOPU111Bit 0EEONUBits 7:3, 1:0 — See 6.2 EEPROM Registers, page 30.NOCOP — COP System Disable
0 = COP enabled (forces reset on time-out)
1 = COP disabled (does not force reset on time-out)
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6 Electrically Erasable Programmable ROM
The MC68HC11F1 has 512 bytes of electrically erasable programmable ROM (EEPROM). A nonvola-tile, EEPROM-based configuration register (CONFIG) controls whether the EEPROM is present or ab-sent and determines its position in the memory map. In single-chip and bootstrap modes the EEPROMis positioned at $FE00–$FFFF. In expanded and special test modes, the EEPROM can be repositionedto any 4-Kbyte boundary ($xE00–$xFFF).
NOTE
EEPROM is available on the MC68HC11F1 only.
6.1 EEPROM Operation
The EEON bit in CONFIG controls whether the EEPROM is present in the memory map. WhenEEON = 1, the EEPROM is enabled. When EEON = 0, the EEPROM is disabled and removed from thememory map. EEON is forced to one out of reset in single-chip and special bootstrap modes to enableEEPROM. EEON is forced to zero out of reset in special test mode to remove EEPROM from the mem-ory map, although test software can turn it back on. In normal expanded mode, EEON is reset to thevalue last programmed into CONFIG.
An on-chip charge pump develops the high voltage required for programming and erasing. When theE-clock frequency is 1 MHz or above, the charge pump is driven by the E-clock. When the E-clock fre-quency is less than 1 MHz, select the internal RC oscillator to drive the EEPROM charge pump by writ-ing one to the CSEL bit in the OPTION register. Refer to the discussion of the OPTION register in 4.3System Initialization Registers, page 23.6.2 EEPROM RegistersBPROT — Block Protect
Bit 70RESET06005004PTCON13BPRT312BPRT211BPRT11Bit 0BPRT01$x035
Bits [7:5] — Not implemented. Reads always return zero and writes have no effect.PTCON — Protect for CONFIG
0 = CONFIG register can be programmed or erased normally1 = CONFIG register cannot be programmed or erasedBPRT[3:0] — Block Protect Bits for EEPROM
0 = Protection disabled1 = Protection enabled
Table 14 Block Protect Bits for EEPROM
Bit NameBPRT3BPRT2PBRT1BPRT0
Block Protected$xEE0–xFFF$xE60–xEDF$xE20–xE5F$xE00–xE1F
Block Size288 Bytes128 Bytes Bytes32 Bytes
NOTE
Block protect register bits can be written to zero (protection disabled) only oncewithin cycles of a reset in normal modes, or at any time in special modes. Blockprotect register bits can be written to one (protection enabled) at any time.
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PPROG — EEPROM Programming Control
Bit 7ODDRESET06EVEN05004BYTE03ROW02ERASE01EELAT0Bit 0EEPGM0$x03B
ODD — Program Odd Rows (TEST)EVEN — Program Even Rows (TEST)
ROW and BYTE — Row Erase Select Bit and Byte Erase Select
The value of these bits determines the manner in which EEPROM is erased. Bit encodings are shownin 6.2 EEPROM Registers, page 30.
Table 15 ROW and BYTE Encodings
BYTE0011
ROW0101
Action
Bulk Erase (All 512 Bytes)Row Erase (16 Bytes)
Byte Erase Byte Erase
ERASE — Erase/Normal Control for EEPROM
0 = Normal read or program mode1 = Erase mode
EELAT — EEPROM Latch Control
0 = EEPROM address and data bus configured for normal reads
1 = EEPROM address and data bus configured for programming or erasingEEPGM — EEPROM Program Command
0 = Program or erase voltage to EEPROM array switched off1 = Program or erase voltage to EEPROM array switched on
CONFIG — EEPROM Mapping, COP, EEPROM Enables $x03F
Bit 7EE3RESETU6EE2U5EE1U4EE0U3112NOCOPU111Bit 0EEONUU = Unaffected by reset.
The CONFIG register is used to assign EEPROM a location in the memory map and to enable or disableEEPROM operation. Bits in this register are user-programmed except when forced to certain values, asnoted in the following bit descriptions.
EE[3:0] — EEPROM Map Position
EEPROM is located at $xE00 – $xFFF, where x is the value represented by these four bits. In single-chip and bootstrap modes, EEPROM is forced to $FE00 – $FFFF, regardless of the state of these bits.On factory-fresh devices, EE[3:0] = $0.Bit 3 — Not implemented. Reads always return one and writes have no effect.NOCOP — COP System Disable
0 = COP enabled (forces reset on time-out)
1 = COP disabled (does not force reset on time-out)
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Bit 1 — Not implemented. Reads always return one and writes have no effect.
EEON — EEPROM Enable
This bit is forced to one in single-chip and bootstrap modes. In test mode, EEON is forced to zero outof reset. In expanded mode, the EEPROM obeys the state of this bit.
0 = EEPROM is removed from the memory map.1 = EEPROM is present in the memory map.
Refer to 6.4 CONFIG Register Programming for instructions on programming this register.6.3 EEPROM Programming and Erasure
Programming and erasing the EEPROM is controlled by the PPROG register, subject to the block pro-tect (BPROT) register value. To erase the EEPROM, ensure that the proper bits of the BPROT registerare cleared, and then complete the following steps:
1.Write to PPROG with the ERASE and EELAT bits set and the BYTE and ROW bits set or
cleared as appropriate.
2.Write to the appropriate EEPROM address with any data. Row erase ($xE00–$xE0F, $xE10–
$xE1F,... $xFF0–$xFFF) requires a single write to any location in the row. Perform bulk eraseby writing to any location in the array.
3.Write to PPROG with the ERASE, EELAT, and EEPGM bits set and the BYTE and ROW bits
set or cleared as appropriate.
4.Delay for 10 ms (20 ms for low-voltage operation).
5.Clear the EEPGM bit in PPROG to turn off the high voltage.
6.Clear the PPROG register to reconfigure EEPROM address and data buses for normal opera-tions.To program the EEPROM, ensure that the proper bits of the BPROT register are cleared, and then com-plete the following steps:
1.
2.3.4.5.6.
Write to PPROG with the EELAT bit set.Write data to the desired address.
Write to PPROG with the EELAT and EEPGM bits set.Delay for 10 ms (20 ms for low-voltage operation).
Clear the EEPGM bit in PPROG to turn off the high voltage.
Clear the PPROG register to reconfigure EEPROM address and data buses for normal opera-tions.
6.3.1 Programming a Byte
The following example shows how to program an EEPROM byte. This example assumes that the ap-propriate bits in BPROT are cleared and that the data to be programmed is present in accumulator A.
PROG
LDABSTABSTAALDABSTABJSRCLR
#$02$103B$FE00#$03$103BDLY10$103B
EELAT=1, EEPGM=0Set EELAT bit
Store data to EEPROM addressEELAT=1, EEPGM=1
Turn on programming voltageDelay 10 ms
Turn off high voltage and set to READ mode
6.3.2 Bulk Erase
The following example shows how to bulk erase the 512-byte EEPROM. The CONFIG register is notaffected in this example. Note that when the CONFIG register is bulk erased, CONFIG and the 512-bytearray are all erased.
BULKE
LDABSTAB
#$06$103B
ERASE=1, EELAT=1, EEPGM=0Set EELAT bit
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STABLDABSTABJSRCLR
$FE00#$07$103BDLY10$103B
Store any data to any EEPROM addressEELAT=1, EEPGM=1
Turn on programming voltageDelay 10 ms
Turn off high voltage and set to READ mode
6.3.3 Row Erase
The following example shows how to perform a fast erase of large sections of EEPROM. This exampleassumes that index register X contains the address of a location in the desired row.
ROWE
LDABSTABSTABLDABSTABJSRCLR
#$0E$103B$xxxx#$0F$103BDLY10$103B
ROW=1, ERASE=1, EELAT=1, EEPGM=0Set to ROW erase mode
Store any data to any address in ROWROW=1, ERASE=1, EELAT=1, EEPGM=1Turn on high voltageDelay 10 ms
Turn off high voltage and set to READ mode
6.3.4 Byte Erase
The following is an example of how to erase a single byte of EEPROM. This example assumes that in-dex register X contains the address of the byte to be erased.
BYTEE
LDABSTABSTABLDABSTABJSRCLR
#$16$103B$0,X#$17$103BDLY10$103B
BYTE=1, ROW=0, ERASE=1, EELAT=1, EEPGM=0Set to BYTE erase mode
Store any data to address to be erasedBYTE=1, ROW=0, ERASE=1, EELAT=1, EEPGM=1Turn on high voltageDelay 10 ms
Turn off high voltage and set to READ mode
6.4 CONFIG Register Programming
Because the CONFIG register is implemented with EEPROM cells, use EEPROM procedures to eraseand program this register. The procedure for programming is the same as for programming a byte inthe EEPROM array, except that the CONFIG register address is used. CONFIG can be programmed orerased (including byte erase) while the MCU is operating in any mode, provided that PTCON in BPROTis clear. To change the value in the CONFIG register, complete the following procedure. Do not initiatea reset until the procedure is complete. The new value will not take effect until after the next reset se-quence.
1.Erase the CONFIG register.
2.Program the new value to the CONFIG address. 3.Initiate reset.
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7 Parallel Input/Output
On the MC68HC11F1, either 54 or 51 pins are available for general-purpose I/O, depending on thepackage. These pins are arranged into ports A, B, C, D, E, F, and G. On the MC68HC11FC0, either 52or 49 pins are available, depending on the package.
I/O functions on some ports (B, C, F, and G) are affected by the mode of operation selected. In the sin-gle-chip and bootstrap modes, they are configured as parallel I/O data ports. In expanded and testmodes, they are configured as follows:
• Ports B and F are configured as the address bus.• Port C is configured as the data bus.
• Port G bit 7 is configured as the optional program chip select CSPROG. In addition, in expanded and test modes the R/W signal is configured as data bus direction control. Theremaining ports (A, D, and E) are unaffected by mode changes.7.1 Port A
Port A is an eight-bit general-purpose I/O port (PA[7:0]) with a data register (PORTA) and a data direc-tion register (DDRA). Port A pins are available for shared use among the main timer, pulse accumulator,and general I/O functions, regardless of mode. Four pins can be used for timer output compare func-tions (OC), three for input capture (IC), and one as either a fourth IC or a fifth OC.7.2 Port B
Port B is an eight-bit general-purpose output-only port in single-chip modes. In expanded modes, portB pins act as high-order address lines ADDR[15:8], and accesses to PORTB (the port B data register)are mapped externally. 7.3 Port C
Port C is an eight-bit general-purpose I/O port with a data register (PORTC) and a data direction register(DDRC). In single-chip modes, port C pins are general-purpose I/O pins PC[7:0]. Port C can be config-ured for wired-OR operation in single-chip modes by setting the CWOM bit in the OPT2 register. In ex-panded modes, port C is the data bus DATA[7:0], and accesses to PORTC (the port C data register)are mapped externally.7.4 Port D
Port D is a six-bit general-purpose I/O port with a data register (PORTD) and a data direction register(DDRD). In all modes, the six port D lines (PD[5:0]) can be used for general-purpose I/O or for the serialcommunications interface (SCI) or serial peripheral interface (SPI) subsystems. Port D can also be con-figured for wired-OR operation.7.5 Port E
Port E is an eight-bit input-only port that is also used (on the MC68HC11F1 only) as the analog inputport for the analog-to-digital converter. Port E pins that are not used for the A/D system can be used asgeneral-purpose inputs. However, PORTE should not be read during the sample portion of an A/D con-version sequence.
NOTE
PE7 and PE0 are not available on the 80-pin MC68HC11FC0. PE7, PE4, and PE0are not available on the -pin MC68HC11FC0.
7.6 Port F
Port F is an eight-bit output-only port. In single-chip mode, port F pins are general-purpose output pinsPF[7:0]. In expanded mode, port F pins act as low-order address outputs ADDR[7:0].
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7.7 Port G
Port G is an eight-bit general-purpose I/O port with a data register (PORTG) and a data direction register(DDRG). When enabled, the upper four lines (PG[7:4] can be used as chip-select outputs in expandedmodes. When any of these pins are not being used for chip selects, they can be used for general-pur-pose I/O. Port G can be configured for wired-OR operation by setting the GWOM bit in the OPT2 reg-ister.
NOTE
PG[1:0] are not available on the -pin MC68HC11FC0.
7.8 Parallel I/O Registers
Port pin function is mode dependent. Do not confuse pin function with the electrical state of the pin atreset. Port pins are either driven to a specified logic level or are configured as high impedance inputs.I/O pins configured as high-impedance inputs have port data that is indeterminate. The contents of thecorresponding latches are dependent upon the electrical state of the pins during reset. In port descrip-tions, an “I” indicates this condition. Port pins that are driven to a known logic level during reset areshown with a value of either one or zero. Some control bits are unaffected by reset. Reset states forthese bits are indicated with a “U”.PORTA — Port A Data Register
Bit 7PA7RESET:Alternate Function:And/or:IPAIOC16PA6IOC2OC15PA5IOC3OC14PA4IOC4OC13PA3IOC5/IC4OC12PA2IIC1 — 1PA1IIC2 — Bit 0PA0IIC3 — $x000
I = Indeterminate value
DDRA — Port A Data Direction Register
Bit 7DDA7
RESET:
0
6DDA60
5DDA50
4DDA40
3DDA30
2DDA20
1DDA10
Bit 0DDA00
$x001
For DDRx bits, 0 = input and 1 = output.PORTG — Port G Data Register
Bit 7PG7RESET:Alternate Function:ICSPROG6PG6ICSGEN5PG5ICSIO14PG4ICSIO23PG3I2PG2I1PG1*IBit 0PG0*I$x002
*These bits are not present on the -pin QFP version of the MC68HC11FC0.I = Indeterminate value
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DDRG — Port G Data Direction Register $x003
Bit 7DDG7*RESET:06DDG605DDG504DDG403DDG302DDG201DDG10Bit 0DDG00* Following reset in expanded and test modes, PG7/CSPRG is configured as a program chip select, forcing the pinto be an output pin, even though the value of the DDG7 bit remains zero.
For DDRx bits, 0 = input and 1 = output.PORTB — Port B Data Register
Bit 7PB7RESET:06PB60ADDR145PB50ADDR134PB40ADDR123PB30ADDR112PB20ADDR101PB10ADDR9Bit 0PB00ADDR8$x004
Alternate ADDR15Function:The reset state of port B is mode dependent. In single-chip or bootstrap modes, port B pins are general-purpose outputs. In expanded and test modes, port B pins are high-order address outputs and PORTBis not in the memory map.PORTF — Port F Data Register
PF7
RESET:Alternate Function:
0ADDR7
PF60ADDR6
PF50ADDR5
PF40ADDR4
PF30ADDR3
PF20ADDR2
PF10ADDR1
PF00ADDR0
$x005
The reset state of port F is mode dependent. In single-chip or bootstrap modes, port F pins are general-purpose outputs. In expanded and test modes, port F pins are low-order address outputs and PORTFis not in the memory map.PORTC — Port C Data Register
Bit 7PC7
RESET:Alternate Function:
IDATA7
6PC6IDATA6
5PC5IDATA5
4PC4IDATA4
3PC3IDATA3
2PC2IDATA2
1PC1IDATA1
Bit 0PC0IDATA0
$x006
The reset state of port C is mode dependent. In single-chip and bootstrap modes, port C pins are high-impedance inputs. In expanded or test modes, port C pins are data bus inputs/outputs and PORTC isnot in the memory map. The R/W signal is used to control the direction of data transfers.DDRC — Port C Data Direction Register
Bit 7DDC7
RESET:
0
6DDC60
5DDC50
4DDC40
3DDC30
2DDC20
1DDC10
Bit 0DDC00
$x007
For DDRx bits, 0 = input and 1 = output.
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PORTD — Port D Data Register
Bit 70
RESET:Alternate Function:
0 —
600 —
5PD5I
4PD4I
3PD3IMOSI
2PD2IMISO
1PD1ITxD
Bit 0PD0IRxD
$x008
SS SCKDDRD — Port D Data Direction Register
Bit 70
RESET:
0
600
5DDD50
4DDD40
3DDD30
2DDD20
1DDD10
Bit 0DDD00
$x009
For DDRx bits, 0 = input and 1 = output.
NOTE
When the SPI system is in slave mode, DDD5 has no meaning or effect. When theSPI system is in master mode, DDD5 determines whether bit 5 of PORTD is an er-ror detect input (DDD5 = 0) or a general-purpose output (DDD5 = 1). If the SPI sys-tem is enabled and expects one or more of bits [4:2] to be inputs, those bits will beinputs regardless of the state of the associated DDR bits. If one or more of bits [4:2]are expected to be outputs, those bits will be outputs only if the associated DDRbits are set.
PORTE — Port E Data
Bit 7PE71
RESET:Alternate Function
UAN7
6PE6UAN6
5PE5UAN5
4PE42UAN4
3PE3UAN3
2PE2UAN2
1PE1UAN1
Bit 0PE01UAN0
$x00A
NOTES:
1. These bits are not present on the MC68HC11FC0 and will always read zero.
2. This bit is not present on the -pin QFP version of the MC68HC11FC0 and will always read zero.U = Unaffected by rest.
PORTE is an input-only register. Reads return the digital state of the I/O pins, and writes have no effect.On the MC68HC11F1, port E is shared with the analog-to-digital converter. (The A/D converter is notpresent on the MC68HC11FC0.)
OPT2 — System Configuration Option Register 2
Bit 7GWOMRESET06CWOM05CLK4X14LIRDV03—02SPRBYP01—0Bit 0—0$x038
GWOM — Port G Wired-OR Mode Option
This bit affects all port G pins together.
0 = Port G outputs are normal CMOS outputs1 = Port G outputs act as open-drain outputs
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CWOM — Port C Wired-OR Mode Option
This bit affects all port C pins together.
0 = Port C outputs are normal CMOS outputs1 = Port C outputs act as open-drain outputsCLK4X — 4XCLK Output Enable
Refer to 4.3 System Initialization Registers, page 23LIRDV — Load Instruction Register Driven
Refer to 4.3 System Initialization Registers, page 23
Bits 3, 1, 0 — Not implemented. Reads always return zero and writes have no effect.SPRBYP — Refer to 10.2 SPI Registers, page 52.
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8 Chip-Selects
Chip selects eliminate the need for additional external components to interface with peripherals in ex-panded non-multiplexed modes. Chip-select registers control polarity, address block size, base ad-dress, and clock stretching.8.1 Chip-Select Operation
There are four programmable chip selects on the MC68HC11F1 and MC68HC11FC0: two for externalI/O (CSIO1 and CSIO2), one for external program space (CSPROG), and one general-purpose chip se-lect (CSGEN).
CSPROG is active low and becomes active at address valid time. CSPROG is enabled by the PCSENbit of the chip-select control register (CSCTL). Its address block size is selected by the PSIZA andPSIZB bits of CSCTL.
Use the I/O chip selects (CSIO1 and CSIO2) for external I/O devices. These chip-select addresses arefound in the memory map block that contains the status and control registers. CSIO1 is mapped from$x060 to $x7FF, and CSIO2 is mapped from $x800 to $xFFF, where x represents the REG[3:0] bits ofthe INIT register on the MC68HC11F1 or the REG[1:0] bits of the INIT register on the MC68HC11FC0.Polarity and enable-disable selections are controlled by CSCTL register bits IO1EN, IO1PL, IO2EN, andIO2PL. The IO1AV and IO2AV bits of the CSGSIZ register determine whether the chip selects are validduring address or E-clock valid times.
The general-purpose chip select is the most flexible of the four chip selects. Polarity, valid assertiontime, and block size are determined by the GNPOL, GAVLD, GSIZA, GSIZB, and GSIZC bits of theCSGSIZ register. The starting address is selected with the CSGADR register.
Each of the four chip selects has two associated bits in the chip-select clock stretch register (CSSTRH).These bits allow clock stretching from zero to three cycles (full E-clock periods) to accommodate slowdevice interfaces. Any of the chip selects can be programmed to cause a clock stretch to occur onlyduring access to addresses that fall within that particular chip select’s address range.
During the stretch period, the E-clock is held high and the bus remains in the state that it is normally inat the end of E high time. Internally, the clocks continue to run, which maintains the integrity of the timersand baud-rate generators.
Priority levels are assigned to prevent the four chip selects from conflicting with each other or with in-ternal memory and registers. There are two sets of priorities controlled by the value of the general-pur-pose chip-select priority bit (GCSPR) of the CSCTL register. Refer to Table 17.8.2 Chip-Select RegistersCSSTRH — Clock Stretching
Bit 7IO1SARESET:06IO1SB05IO2SA04IO2SB03GSTHA02GSTHB01PSTHA0Bit 0PSTHB0$x05C
IO1SA, IOS1B — I/O Chip-Select 1 Clock StretchIO2SA, IO2SB — I/O Chip-Select 2 Clock Stretch
GSTHA, GSTHB — General-Purpose Chip-Select Clock Stretch
PSTHA, PSSTHB — Program Chip-Select Clock Stretch
Each pair of bits selects the number of clock cycles of stretch for the corresponding chip select.
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Table 16 Chip Select Clock Stretch Control
Clock Stretch Bits A, B
0 00 11 01 1
Clock Stretch0 Cycles1 Cycle2 Cycles3 Cycles
CSCTL — Chip-Select Control
Bit 7IO1ENRESET:06IO1PL05IO2EN04IO2PL03GCSPR02PCSEN*—1PSIZA0Bit 0PSIZB0$x05D
* PCSEN is set out of reset in expanded modes and cleared in single-chip modes.
IO1EN — I/O Chip-Select 1 Enable
0 = CSIO1 disabled1 = CSIO1 enabledIO1PL — I/O Chip-Select 1 Polarity
0 = CSIO1 active low1 = CSIO1 active highIO1EN — I/O Chip-Select 2 Enable
0 = CSIO2 disabled1 = CSIO2 enabledIO2PL — I/O Chip-Select 2 Polarity
0 = CSIO2 active low1 = CSIO2 active high
GCSPR — General-Purpose Chip-Select Priority
0 = Program chip-select has priority over general-purpose chip-select1 = General-purpose chip-select has priority over program chip-selectRefer to Table 17.
Table 17 Chip Select Priorities
GCSPR = 0
On-Chip RegistersOn-Chip RAMBootloader ROMOn-Chip EEPROM1I/O Chip SelectsProgram Chip SelectGeneral-Purpose Chip Select
GCSPR = 1
On-Chip RegistersOn-Chip RAMBootloader ROMOn-Chip EEPROM1I/O Chip Selects
General-Purpose Chip SelectProgram Chip Select
NOTES:
1. EEPROM is present on the MC68HC11F1 only.
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PCSEN — Program Chip-Select Enable
Reset clears PCSEN in single-chip modes and sets PCSEN in expanded modes.
0 = CSPROG disabled1 = CSPROG enabledPSIZA, PSIZB — Select Size of Program Chip-Select
Table 18 Program Chip Select Size Control
PSIZA0011
PSIZB0101
Size Kbytes32 Kbytes16 Kbytes8 Kbytes
Address Range$0000–$FFFF$8000–$FFFF$C000–$FFFF$E000–$FFFF
CSGADR — General-Purpose Chip-Select Address Register
Bit 7GA15RESET:06GA1405GA1304GA1203GA1102GA1001—$x05E
Bit 0—00GA[15:10] — General-Purpose Chip-Select Starting Address
These bits determine the starting address of the CSGEN valid address space and correspond to thehigh-order address bits ADDR[15:10]. Table 19 illustrates how the block size selected determineswhich of this register's bits are valid.
Table 19 General Purpose Chip Select Starting Address
CSGEN Block Size
0 Kbytes1 Kbyte2 Kbytes4 Kbytes8 Kbytes16 Kbytes32 Kbytes Kbytes
CSGADR Bits Valid
NoneGA15 – GA10GA15 – GA11GA15 – GA12GA15 – GA13GA15 – GA14
GA15None
Bits [1:0] — Not implemented. Reads always return zero and writes have no effect.
CSGSIZ — General-Purpose Chip-Select Size Register $x05F
Bit 7IO1AVRESET:06IO2AV05—04GNPOL03GAVLD02GSIZA11GSIZB1Bit 0GSIZC1IO1AV — I/O Chip-Select 1 Address Valid
0 = CSIO1 is valid during E-clock valid time (E-clock high)1 = CSIO1 is valid during address valid timeIO2AV — I/O Chip-Select 2 Address Valid
0 = CSIO2 is valid during E-clock valid time (E-clock high)1 = CSIO2 is valid during address valid time
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Bit 5 — Not implemented. Reads always return zero and writes have no effect.GNPOL — General-Purpose Chip-Select Polarity
0 = CSGEN is active low1 = CSGEN is active high
GAVLD — General-Purpose Chip-Select Address Valid
0 = CSGEN is valid during E-clock valid time (E-clock high)1 = CSGEN is valid during address valid timeGSIZ[A:C] — Block Size for CSGEN
Refer to Table 20 for bit values.
Table 20 General-Purpose Chip Select Size Control
GSIZ[A:C]
000001010011100101110111
Address Size Kbytes32 Kbytes16 Kbytes8 Kbytes4 Kbytes2 Kbytes1 Kbyte0 Kbytes (disabled)
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9 Serial Communications Interface (SCI)
The SCI, a universal asynchronous receiver transmitter (UART) serial communications interface, is oneof two independent serial I/O subsystems in the MC68HC11F1 and MC68HC11FC0. The SCI has astandard non-return to zero (NRZ) format (one start bit, eight or nine data bits, and one stop bit) andseveral selectable baud rates. The transmitter and receiver are independent but use the same data for-mat and bit rate.9.1 SCI Block Diagrams
TRANSMITTERBAUD RATECLOCK(WRITE ONLY)DDD1 SCDR Tx BUFFER10 (11) - BIT Tx SHIFT REGISTERH(8)76543210LPIN BUFFERAND CONTROLPD1TxDSHIFT ENABLEJAM ENABLETRANSFER Tx BUFFERPREAMBLE—JAM 1sBREAK—JAM 0sSIZE 8/9TRANSMITTERCONTROL LOGICFORCE PINDIRECTION (OUT)WAKETDRETCRDRFIDLEORR8NFT8SCCR1 SCI CONTROL 1SCSR1 SCI STATUS 1TDRETIETCTCIETCIERWUSBKFEILIERIEMTIESCCR2 SCI CONTROL 2SCI RxQUESTSSCI INTERRUPTREQUEST
TEREINTERNALDATA BUS
Figure 9 SCI Transmitter Block Diagram
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RECEIVERBAUD RATECLOCKDDD0÷16STOP10 (11) - BIT Rx SHIFT REGISTER87654MSBDISABLEDRIVERRE3210ALLONESSTARTL Rx BUFFER(READ ONLY)PD0RxDPIN BUFFERAND CONTROLDATARECOVERYHWAKEUPLOGICRDRFIDLEWAKEORNFTDRER8T8SCCR1 SCI CONTROL 1TCMSCSR1FE SCI STATUS 1SCDRRDRFRIEIDLEILIEORRIERWUTCIEILIERIERESBKTIETESCCR2 SCI CONTROL 2SCI TxSCI INTERRUPTREQUESTSREQUEST
INTERNAL
DATA BUS
Figure 10 SCI Receiver Block Diagram
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9.2 SCI RegistersBAUD — Baud Rate
Bit 7TCLRRESET:06SCP2 05SCP104SCP003RCKB02SCR2U1SCR1UBit 0SCR0U$x02B
TCLR — Clear Baud Rate Counters (TEST)
Bit 6 — Not implemented. Reads always return zero and writes have no effect.RCKB — SCI Baud-Rate Clock Check (TEST)
SCP[2:0] — SCI Baud Rate Prescaler Selects
These bits determine the baud rate prescaler frequency. Refer to Table 21 and Figure 11.SCR[2:0] — SCI Baud Rate Selects
These bits determine the receiver and transmitter baud rate. Refer to Table 22 and Figure 11.
Table 21 Baud Rate Prescaler Selection
SCP[2:0] X00 001 X10X11101
Divide Internal Clock By
134139
Prescaler Output1
XTAL = XTAL = 4.0 MHz4.9152 MHz6250020833156254800—
7680025600192005908—
XTAL = XTAL = XTAL = XTAL = XTAL = XTAL = 8.0 MHz10.0 MHz12.0 MHz16.0 MHz20.0 MHz24.0 MHz1250004166731250—
1562505208338400—
18750062500468751442320830
250000833336250019200—
3125001041677680024038—
3750001250009375028846—
9600 12019NOTES:
1. A blank table cell indicates that an uncommon rate results.
Table 22 Baud Rate Selection
Baud Rate
SCR[2:0]
Divide Prescaler By
12481632128
Prescaler Output = 480048002400120060030015075—
Prescaler Output = 9600960048002400120060030015075
Prescaler Output = 19200192009600480024001200600300150
Prescaler Output = 3840038400192009600480024001200600300
Prescaler Output = 768007680038400192009600480024001200600
0 0 00 0 10 1 00 1 11 0 01 0 11 1 01 1 1
The prescaler bits SCP[2:0] determine the highest baud rate, and the SCR[2:0] bits select an additionalbinary submultiple (divide by 1, 2, 4,..., through 128) of this highest baud rate. The result of these twodividers in series is the 16X receiver baud rate clock. The SCR[2:0] bits are not affected by reset andcan be changed at any time. They should not be changed, however, when an SCI transfer is in progress.
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Figure 11 illustrates the SCI baud rate timing chain. The prescaler select bits determine the highestbaud rate. The rate select bits determine additional divide-by-two stages to arrive at the receiver timing(RT) clock rate. The baud rate clock is the result of dividing the RT clock by 16.
EXTALOSCILLATORANDCLOCK GENERATOR(÷4)÷ 3EX00INTERNAL BUS CLOCK (PH2)XTAL÷ 4001X10÷ 13X11÷ 9101SCR[2:0]0:0:0÷ 20:0:1÷ 20:1:0÷ 20:1:1÷ 21:0:0÷ 21:0:1÷ 21:1:0÷ 21:1:1SCI Receive Baud Rate (16x)÷ 16SCI Transmit Baud Rate (1x)Figure 11 SCI Baud Rate Generator Block Diagram
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SCCR1 — SCI Control Register 1 $x02C
Bit 7R8RESET:U6T8U5004M03WAKE0200100Bit 000U = Unaffected by reset
R8 — Receive Data Bit 8
If M is set, R8 stores the ninth bit of the receive data character.T8 — Transmit Data Bit 8
If M is set, T8 stores the ninth bit of the transmit data character.
Bit 5 — Not implemented. Reads always return zero and writes have no effect.M — Mode (Select Character Format)
0 = 1 start bit, 8 data bits, 1 stop bit1 = 1 start bit, 9 data bits, 1 stop bitWAKE — Wake Up by Address Mark/Idle
0 = Wake up by IDLE line recognition1 = Wake up by address mark
Bits [2:0] — Not implemented. Reads always return zero and writes have no effect.
SCCR2 — SCI Control Register 2 $x02D
Bit 7TIERESET:06TCIE05RIE04ILIE03TE02RE01RWU0Bit 0SBK0TIE — Transmit Interrupt Enable
0 = TDRE interrupts disabled
1 = SCI interrupt requested when the TDRE flag is setTCIE — Transmit Complete Interrupt Enable
0 = TC interrupts disabled
1 = SCI interrupt requested when the TC flag is set
RIE — Receiver Interrupt Enable
0 = RDRF and OR interrupts disabled
1 = SCI interrupt requested when the RDRF flag or the OR flag is setILIE — Idle Line Interrupt Enable
0 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
TE — Transmitter Enable
When TE goes from zero to one, one unit of idle character time (logic one) is queued as a preamble.
0 = Transmitter disabled1 = Transmitter enabledRE — Receiver Enable
0 = Receiver disabled1 = Receiver enabled
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RWU — Receiver Wake Up Control
0 = Normal SCI receiver
1 = Wake up enabled and receiver interrupt inhibitedSBK — Send Break
0 = Break generator off
1 = Break codes generated as long as SBK = 1
SCSR — SCI Status Register $x02E
Bit 7TDRERESET:16TC15RDRF04IDLE03OR02NF01FE0Bit 000TDRE — Transmit Data Register Empty Flag
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR with TDRE set and thenwriting to SCDR.
0 = SCDR is busy1 = SCDR is empty TC — Transmit Complete Flag
This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clearthe TC flag by reading SCSR with TC set and then writing to SCDR.
0 = Transmitter is busy1 = Transmitter is idleRDRF — Receive Data Register Full Flag
This flag is set if a received character is ready to be read from SCDR. Clear the RDRF flag by readingSCSR with RDRF set and then reading SCDR.
0 = SCDR empty1 = SCDR fullIDLE — Idle Line Detected Flag
This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD line has beenactive and becomes idle again. The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSRwith IDLE set and then reading SCDR.
0 = RxD line is active1 = RxD line is idleOR — Overrun Error Flag
OR is set if a new character is received before a previously received character is read from SCDR. ClearOR by reading SCSR with OR set and then reading SCDR.
0 = No overrun detected1 = Overrun detected NF — Noise Error Flag
NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by readingSCSR with NF set and then reading SCDR.
0 = Unanimous decision1 = Noise detectedFE — Framing Error
FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SCSRwith FE set and then reading SCDR.
0 = Stop bit detected1 = Zero detected
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Bit 0 — Not implemented. Reads always return zero and writes have no effect.SCDR — Serial Communications Data Register
Bit 7Bit 7RESET:I66I55I44I33I22I12IBit 0Bit 0I$x02F
I = Indeterminate value
Reading SCDR retrieves the last byte received in the receive data buffer. Writing to SCDR loads thetransmit data buffer with the next byte to be transmitted.
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10 Serial Peripheral Interface
The serial peripheral interface (SPI) allows the MCU to communicate synchronously with peripheral de-vices and other microprocessors. The SPI protocol facilitates rapid exchange of serial data between de-vices in a control system. The MC68HC11F1 and MC68HC11FC0 can be set up for master or slaveoperation. Standard data rates can be as high as one half of the E-clock rate when configured as mas-ter, and as fast as the E-clock when configured as slave.
The MC68HC11FC0 has an additional control bit that allows the SPI baud rate counter to be bypassed.This allows a master mode baud rate equal to the E-clock frequency.10.1 SPI Block Diagram
SPI STATUS REGISTERDOTTED LINE CONNECTIONSPRESENT ON MC68HC11FC0 ONLYWCOLMODFSPIFSPI CONTROL REGISTERSPIESPEDWOMMSTRCPHACPOLSPR1SPR0SPIESPEMSTRSPIFWCOLMODFSPICONTROLSPI INTERRUPTREQUESTSPEDWOMMSTRINTERNAL DATA BUSSSPD5÷2÷4÷16÷32DIVIDERSELECTMSTRCPHACPOLSPR0SPR1INTERNALMCU CLOCKSYSTEM CONFIGURATIONOPTION 2 REGISTERSMPIN CONTROL LOGICCLOCK LOGICCLOCKMSSCKPD4MOSIPD3SPRBYPMSBLSB8-BIT SHIFT REGISTERREAD DATA BUFFERMSMISOPD2Figure 12 SPI Block Diagram
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10.2 SPI Registers
SPCR — SPI Control Register
Bit 7SPIERESET:06SPE05DWOM04MSTR03CPOL02CPHA11SPR1UBit 0SPR0U$x028
U = Unaffected by reset
SPIE — SPI Interrupt Enable
When SPI interrupts are enabled, a hardware interrupt sequence is requested each time the SPIF orMODF status flag is set. SPI interrupts are inhibited if this bit is cleared or if the I bit in the condition coderegister is one.
0 = SPI interrupt disabled1 = SPI interrupt enabledSPE — SPI Enable
When the SPE bit is set, PD[5:2] are dedicated to the SPI function. If the SPI is in master mode and theDDRD bit 5 is set, then PD5/SS becomes a general-purpose output instead of the SS input.0 = SPI off1 = SPI onDWOM — Port D Wired-OR Mode Option for SPI Pins PD[5:2]
0 = Normal CMOS outputs1 = Open-drain outputsMSTR — Master Mode Select
0 = Slave mode 1 = Master mode
CPOL — Clock Polarity
When the clock polarity bit is cleared and data is not being transferred, the SCK pin of the master devicehas a steady state low value. When CPOL is set, SCK idles high. Refer to Figure 13.CPHA — Clock Phase
The clock phase bit, in conjunction with the CPOL bit, controls the clock-data relationship between mas-ter and slave. The CPHA bit selects one of two clocking protocols. Refer to Figure 13.
SCK CYCLE #(FOR REFERENCE)SCK (CPOL = 0)SCK (CPOL = 1)SAMPLE INPUT(CPHA = 0) DATA OUTSAMPLE INPUT(CPHA = 1) DATA OUTMSB654321LSBMSB654321LSB12345678SS (TO SLAVE)Figure 13 SPI Data Clock Timing Diagram
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SPR[1:0] — SPI Clock Rate Selects
These two bits select the SPI clock (SCK) rate when the device is configured as a master. When thedevice is configured as a slave, the bits have no effect. Refer to Table 23.
Table 23 SPI Baud Rates
Input Frequency1 MHz2 MHz3 MHz4 MHz5 MHz6 MHzAny E
SPR[1:0] = 00500 kbps1 Mbps1.5 Mbps2 Mbps2.5 Mbps3 MbpsE/2
SPR[1:0] = 01250 kbps500 kbps750 kbps1 Mbps1.25 Mbps1.5 MbpsE/4
SPR[1:0] = 1062.5 kbps125 kbps187.5 kbps250 kbps312.5 kbps375 kbpsE/16
SPR[1:0] = 1131.25 kbps62.5 kbps93.75 kbps125 kbps156.25 kbps187.5 kbpsE/32
NOTE
The SPRBYP bit in OPT2 on the MC68HC11FC0 allows the SPI baud rate counterto be bypassed. This permits a maximum master mode baud rate equal to the E-clock frequency on the MC68HC11FC0. SPRBYP is not present on theMC68HC11F1.
SPSR — SPI Status Register
Bit 7SPIFRESET:06WCOL05004MODF0300200100Bit 000$x029
SPIF — SPI Transfer Complete Flag
SPIF is set when an SPI transfer is complete. It is cleared by reading SPSR with SPIF set, followed bya read or write of SPDR.WCOL — Write Collision
WCOL is set when SPDR is written while a transfer is in progress. It is cleared by reading SPSR withWCOL set, followed by a read or write of SPDR.
0 = No write collision1 = Write collisionBit 5 — Not Implemented. Reads always return zero and writes have no effect.
MODF — Mode Fault
A mode fault terminates SPI operation. Set when SS is pulled low while MSTR = 1. MODF is clearedby reading SPSR read with MODF set, followed by a write to SPCR.
0 = No mode fault1 = Mode faultBits [3:0] — Not Implemented. Reads always return zero and writes have no effect.SPDR — SPI Data Register
Bit 7Bit 7665544332211Bit 0Bit 0$x02A
Incoming SPI data is double buffered. Outgoing SPI data is single buffered.
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OPT2 — System Configuration Option Register 2
Bit 7GWOMRESET06CWOM05CLK4X14LIRDV03—02SPRBYP01—0Bit 0—0$x038
Bits [7:4] — See 4.3 System Initialization Registers, page 22.
Bits 3, 1, 0 — Not implemented. Reads always return zero and writes have no effect.
SPRBYP — SPI Baud Rate Counter Bypass
0 = Enable SPI baud rate counter1 = Bypass SPI baud rate counter
When the SPI baud rate counter is bypassed, the SPI can transmit at a maximum master mode baudrate equal to the E-clock frequency. SPRBYP is present only on the MC68HC11FC0 and overridesthe setting of SPR[1:0] in SPCR.
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11 Analog-to-Digital Converter
The MC68HC11F1 analog-to-digital (A/D) converter system uses an all-capacitive charge-redistributiontechnique to convert analog signals to digital values. The A/D system is an 8-channel, 8-bit, multiplexed-input, successive-approximation converter, accurate to ±1 least significant bit (LSB). Because the ca-pacitive charge redistribution technique used includes a built-in sample-and-hold, no external sample-and-hold is required.
Dedicated lines VRH and VRL provide the reference supply voltage inputs. Systems operating at clockrates of 750 kHz or below must use an internal RC oscillator. The CSEL bit in the OPTION register se-lects the clock source for the A/D system. (The CSEL bit is described in 11.3 A/D Registers, page 56.) A multiplexer allows the single A/D converter to select one of 16 analog signals, as shown in Table 24.
NOTE
The A/D converter is present on the MC68HC11F1 only.
PE0AN0PE1AN1PE2AN2PE3AN3PE4AN4PE5AN5PE6AN6ANALOGMUX8-BIT CAPACITIVE DACWITH SAMPLE AND HOLDVRHVRLSUCCESSIVE APPROXIMATIONREGISTER AND CONTROLRESULTINTERNALDATA BUSCCFSCANMULTCDCCCBPE7AN7ADCTL A/D CONTROLRESULT REGISTER INTERFACEADR1 A/D RESULT 1ADR2 A/D RESULT 2ADR3 A/D RESULT 3ADR4 A/D RESULT 4CAEA9 A/D BLOCKFigure 14 A/D Converter Block Diagram
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11.1 Input Pins
Port E pins can also be used as digital inputs. Reads of port E pins are not recommended during thesample portion of an A/D conversion cycle, when the gate signal to the N-channel input gate is on. Be-cause no P-channel devices are directly connected to either input pins or reference voltage pins, volt-ages above VDD do not cause a latchup problem, although current should be limited according tomaximum ratings. Figure 15 is a functional diagram of an input pin.
ANALOGINPUTPINDIFFUSION/POLYCOUPLER+ ~20V– ~0.7V+ ~12V– ~0.7VDUMMY N-CHANNELOUTPUT DEVICE< 2 pF≤ 4 KΩ400 nAJUNCTIONLEAKAGE*~ 20 pFDAC
CAPACITANCE INPUTPROTECTIONDEVICEVRL
* THIS ANALOG SWITCH IS CLOSED ONLY DURING THE 12-CYCLE SAMPLE TIME.
Figure 15 Electrical Model of an Analog Input Pin (Sample Mode)
11.2 Conversion Sequence
A/D converter operations are performed in sequences of four conversions each. A conversion sequencecan be repeated continuously or stop after one iteration. The conversion complete flag (CCF) is set afterthe fourth conversion in a sequence to show the availability of data in the result registers. Figure 16shows the timing of a typical sequence. Synchronization is referenced to the system E clock.
E CLOCK
MSB4CYCLESBIT 62CYCBIT 52CYCBIT 42CYCBIT 32CYCBIT 22CYCBIT 12CYCLSB2CYC2CYCEND12 E CYCLESWRITE TO ADCTLSAMPLE ANALOG INPUTSUCCESSIVE APPROXIMATION SEQUENCE0CONVERT FIRSTCHANNEL, UPDATEADR132CONVERT SECONDCHANNEL, UPDATEADR2CONVERT THIRDCHANNEL, UPDATEADR3CONVERT FOURTHCHANNEL, UPDATE96ADR4128 — E CYCLESFigure 16 A/D Conversion Sequence
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11.3 A/D Registers
ADCTL — A/D Control/Status
Bit 7CCFRESET:I6005SCANI4MULTI3CDI2CCI1CBIBit 0CAI$x030
I = Indeterminate value
CCF — Conversions Complete Flag
A read-only status indicator, this bit is set when all four A/D result registers contain valid conversion re-sults. Each time the ADCTL register is overwritten, this bit is automatically cleared to zero and a con-version sequence is started. In the continuous mode, CCF is set at the end of the first conversionsequence.Bit 6 — Not implemented. Reads always return zero and writes have no effect.SCAN — Continuous Scan Control
0 = Do four conversions and stop
1 = Convert four channels in selected group continuouslyMULT — Multiple Channel/Single Channel Control
0 = Convert single channel selected
1 = Convert four channels in selected group
CD–CA — Channel Select D through A
Refer to Table 24. When a multiple channel mode is selected (MULT = 1), the two least significant chan-nel select bits (CB and CA) have no meaning and the CD and CC bits specify which group of four chan-nels is to be converted.
Table 24 A/D Converter Channel Assignments
Channel Select Control Bits
CD:CC:CB:CA
0000000100100011010001010110011110XX1100110111101111
NOTES:
1. Used for factory testing.
Channel Signal
AN0AN1AN2AN3AN4AN5AN6AN7ReservedVRH1VRL1 (VRH)/21Reserved1
Result in ADRx if MULT = 1
ADR1ADR2ADR3ADR4ADR1ADR2ADR3ADR4ADR1–ADR4
ADR1ADR2ADR3ADR4
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ADR1 – ADR4 — A/D Results
$x031$x032$x033$x034
Bit 7Bit 7Bit 7Bit 7
6666
5555
4444
3333
2222
1111
$x031 – $x034
Bit 0Bit 0Bit 0Bit 0
ADR1ADR2ADR3ADR4
Each read-only result register holds an eight-bit conversion result. Writes to these registers have no ef-fect. Data in the A/D converter result registers is valid when the CCF flag in the ADCTL register is set,indicating a conversion sequence is complete. If conversion results are needed sooner, refer to Figure16, which shows the A/D conversion sequence diagram.
Table 25 Analog Input to 8-Bit Result Translation Table
Bit 7
Percentage1Volts250%2.500
625%1.250
512.5%0.625
46.25%0.3125
33.12%0.1562
21.56%0.0781
1 0.78%0.0391
Bit 00.39%0.0195
NOTES:
1. % of VRH–VRL
2. Volts for VRL = 0; VRH = 5.0 V
OPTION — System Configuration Options
Bit 7ADPURESET:06CSEL05IRQE*04DLY*13CME02FCME*01CR1*0Bit 0CR0*0$x039
*Can be written only once in first cycles out of reset in normal modes, or at any time in special modes.
ADPU — A/D Power Up
0 = A/D powered down1 = A/D powered up
CSEL — Clock Select
0 = A/D and EEPROM use system E-Clock1 = A/D and EEPROM use internal RC clock
Bits [5:0] — Refer to 4.3 System Initialization Registers, page 23.
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12 Main Timer
The main timer is based on a free-running 16-bit counter with a four-stage programmable prescaler. Thetimer drives the three input capture (IC) channels, four output compare (OC) channels, one channel pro-grammable for either IC or OC, and the pulse accumulator (PA). All of these functions share port A. Themain timer also drives the pulse accumulator, real-time interrupt (RTI), and computer operating properly(COP) watchdog circuits.12.1 Timer Operation
The following tables summarize timing periods for various M68HC11 functions derived from the maintimer for several crystal frequencies.
Table 26 Timer Subsystem Count and Overflow Periods
E-Clock Frequency1 MHz2 MHz3 MHz4 MHz5 MHz6 MHzAny E
PR[1:0] = 001 Count1.000 µs0.500 µs0.333 µs0.250 µs0.200 µs0.167 µs1/E
TCNT Overflow65.536 ms32.768 ms21.845 ms16.384 ms13.107 ms10.923 ms216/E
PR[1:0] = 011 Count4.000 µs2.000 µs1.333 µs1.000 µs0.800 µs0.667 µs4/E
TCNT Overflow262.144 ms131.072 ms87.381 ms65.536 ms52.429 ms43.691 ms218/E
PR[1:0] = 101 Count8.000 µs4.000 µs2.667 µs2.000 µs1.600 µs1.333 µs8/E
TCNT Overflow262.144 ms174.763 ms131.072 ms104.858 ms87.381 ms219/E
PR[1:0] = 111 Count
TCNT Overflow1.049 s524.288 ms349.525 ms262.144 ms209.715 ms174.763 ms220/E
524.288 ms16.000 µs
8.000 µs5.333 µs4.000 µs3.200 µs2.667 µs16/E
Table 27 Real-Time Interrupt Periods
E-Clock Frequency1 MHz2 MHz3 MHz4 MHz5 MHz6 MHzAny E
RTR[1:0] = 008.192 ms4.096 ms2.731 ms2.048 ms1.638 ms1.366 ms213/E
RTR[1:0] = 0116.384 ms8.192 ms5.461 ms4.096 ms3.277 ms2.731 ms214/E
RTR[1:0] = 1032.768 ms16.384 ms10.923 ms8.192 ms6.554 ms5.461 ms215/E
RTR[1:0] = 1165.536 ms32.768 ms21.845 ms16.384 ms13.107 ms10.923 ms221/E
Table 28 COP Watchdog Time-Out Periods
E-Clock Frequency1 MHz2 MHz3 MHz4 MHz5 MHz6 MHzAny E
RTR[1:0] = 0032.768 ms16.384 ms10.923 ms8.192 ms6.554 ms5.461 ms215/E
RTR[1:0] = 01131.072 ms65.536 ms43.691 ms32.768 ms26.214 ms21.845 ms217/E
RTR[1:0] = 10524.288 ms262.144 ms174.763 ms131.072 ms104.858 ms87.381 ms219/E
RTR[1:0] = 11
2.097 s1.049 s699.051 ms524.288 ms419.430 ms349.525 ms221/E
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E CLOCKPRESCALERDivide by1, 4, 8 or 16PR1PR016-BIT TIMER BUSTCNT (HI)TCNT (LO)TOITOF16-BIT FREE RUNNINGCOUNTER9InterruptRequestsTo PulseAccumulatorPORT APinsBit 7PA7OC1OC1I16-BIT COMPARATOR =TOC1 (HI)TOC1 (LO)OC1FFOC1OC2I16-BIT COMPARATOR =TOC2 (HI)TOC2 (LO)OC2FFOC2OC3I16-BIT COMPARATOR =TOC3 (HI)TOC3 (LO)OC3FFOC3OC4I16-BIT COMPARATOR =TOC4 (HI)TOC4 (LO)OC4FFOC4I4O5I16-BIT COMPARATOR =TI4O5 (HI)TI4O5 (LO)16-BIT LATCHCLKI4/O516-BIT LATCHTIC1CLK87Bit 66Bit 55Bit 44Bit 3PA3IC4/OC5OC1PA4OC4/OC1PA5OC3/OC1PA6OC2/OC1OC5I4O5FIC4FOC5CFORCIC1I3Bit 2PA2IC1IC1FIC2I (HI)TIC1 (LO)2Bit 1IC3IPA1IC216-BIT LATCHTIC2CLKIC2F (HI)TIC2 (LO)1Bit 0Port APinControl(Note 1)IC/OC BLOCK16-BIT LATCHTIC3CLKIC3FPA0IC3 (HI)TIC3 (LO)TFLG 1StatusFlagsTMSK 1InterruptEnablesNOTE: Registers that control port A action include DDRA, OC1M, OC1D, PACTL, TCTL1 and TCTL2.
Figure 17 Main Timer
MOTOROLA58MC68HC11F1/FC0MC68HC11FTS/D
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12.2 Timer Registers
CFORC — Timer Force Compare
Bit 7FOC1RESET:06FOC205FOC304FOC403FOC50200100Bit 000$x00B
FOCx — Force Output Compare x Action
0 = Not affected
1 = Output compare x action occurs, but OCxF flag bit is not set
Bits [2:0] — Not implemented. Reads always return zero and writes have no effect.
OC1M — Output Compare 1 Mask $x00C
Bit 7OC1M7RESET:06OC1M605OC1M504OC1M403OC1M30200100Bit 000Bits set in OC1M allow OC1 to output the corresponding OC1D bits in port A when a successful com-pare event occurs.
OC1M[7:3] — Output Compare Masks
0 = Control of the corresponding port A pin is disabled1 = Control of the corresponding port A pin is enabled
Bits [2:0] — Not implemented. Reads always return zero and writes have no effect.
OC1D — Output Compare 1 Data $x00D
Bit 7OC1D7RESET:06OC1D605OC1D504OC1D403OC1D30200100Bit 000OC1D[7:3] — Output Compare Data
Data in OC1Dx is output to port A bit x on successful OC1 compares if OC1Mx is set.Bits [2:0] — Not implemented. Reads always return zero and writes have no effect.
TCNT — Timer Count $x00E, $x00F
$x00E$x00FRESET:Bit 15Bit 7014601350124011301020910Bit 8Bit 00HighLowThe 16-bit read-only TCNT register contains the prescaled value of the 16-bit timer. A full counter read
addresses the most significant byte (MSB) first. A read of this address causes the least significant byteto be latched into a buffer for the next CPU cycle so that a double-byte read returns the full 16-bit stateof the counter at the time of the MSB read cycle.
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TIC1–TIC3 — Timer Input Capture $x010–$x015
$x010$x011Bit 15Bit 714613512411310291Bit 8Bit 0HighLow$x012$x013Bit 15Bit 714613512411310291Bit 8Bit 0HighLow$x014$x015Bit 15Bit 714613512411310291Bit 8Bit 0HighLowTICx registers are not affected by reset.
TOC1–TOC4 — Timer Output Compare $x016–$x01D
$x016$x017Bit 15Bit 714613512411310291Bit 8Bit 0HighLow$x018$x019Bit 15Bit 714613512411310291Bit 8Bit 0HighLow$x01A$x01BBit 15Bit 714613512411310291Bit 8Bit 0HighLow$x01C$x01DBit 15Bit 714613512411310291Bit 8Bit 0HighLowAll TOCx register pairs are reset to ones ($FFFF).
TI4/O5 — Timer Input Capture 4/Output Compare 5 $x01E, $x01F
$x01E$x01FBit 15Bit 714613512411310291Bit 8Bit 0HighLowTI4/O5 is reset to ones ($FFFF).TCTL1 — Timer Control 1
Bit 7OM2RESET:06OL205OM304OL303OM402OL401OM50Bit 0OL50$x020
OM2–OM5 — Output Mode
OL2–OL5 — Output Level
Each OMx–OLx bit pair determines the output action taken on the corresponding OCx pin after a suc-cessful compare, as shown in Table 29. OC5 functions only if the I4/O5 bit in the PACTL register iscleared.
MOTOROLA60MC68HC11F1/FC0MC68HC11FTS/D
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Table 29 Output Compare Actions
OMx0011
OLx0101
Action Taken on Successful CompareTimer disconnected from output pin logicToggle OCx output lineClear OCx output line to zeroSet OCx output line to one
TCTL2 — Timer Control 2
Bit 7EDG4BRESET:06EDG4A05EDG1B04EDG1A03EDG2B02EDG2A01EDG3B0Bit 0EDG3A0$x021
EDGxB, EDGxA — Input Capture Edge Control
Each EDGxB, EDGxA pair determines the polarity of the input signal on the corresponding ICx that willtrigger an input capture, as shown in Table 30. IC4 functions only if the I4/O5 bit in the PACTL registeris set.
Table 30 Input Capture Configuration
EDGxB0011
EDGxA0101
Configuration
Capture disabled
Capture on rising edges onlyCapture on falling edges onlyCapture on any edge
TMSK1 — Timer Interrupt Mask 1 $x022
Bit 7OC1IRESET:06OC2I05OC3I04OC4I03I4/O5I02IC1I01IC2I0Bit 0IC3I0Bits in TMSK1 correspond bit for bit with flag bits in TFLG1. Each bit that is set in TMSK1 enables thecorresponding interrupt source.
OCxI — Output Compare x Interrupt Enable
If the OCxI enable bit is set when the OCxF flag bit is set, a hardware interrupt sequence is requested.I4/O5I — Input Capture 4/Output Compare 5 Interrupt Enable
When I4/O5 in PACTL is one, I4/O5I is the input capture 4 interrupt enable bit. When I4/O5 in PACTLis zero, I4/O5I is the output compare 5 interrupt enable bit.ICxI — Input Capture x Interrupt Enable
If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested.TFLG1 — Timer Interrupt Flag 1 $x023
Bit 7OC1FRESET:06OC2F05OC3F04OC4F03I4/O5F02IC1F01IC2F0Bit 0IC3F0Bits in TFLG1 are cleared by writing a one to the corresponding bit positions.
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OCxF — Output Compare x Flag
Set each time the counter matches output compare x value.
I4/O5F — Input Capture 4/Output Compare 5 Flag
Set by IC4 or OC5, depending on which function was enabled by I4/O5 of PACTL.ICxF — Input Capture x Flag
Set each time a selected active edge is detected on the ICx input line.
TMSK2 — Timer Interrupt Mask 2 $x024
Bit 7TOIRESET:06RTII05PAOVI04PAII03002001PR10Bit 0PR00Bits [7:4] in TMSK2 correspond bit for bit with flag bits in TFLG2. Setting any of these bits enables thecorresponding interrupt source. TMSK2 can be written only once in the first cycles out of reset innormal modes, or at any time in special modes.TOI — Timer Overflow Interrupt Enable
0 = Timer overflow interrupt disabled1 = Interrupt requested when TOF is setRTII — Real-Time Interrupt Enable
0 = Real-time interrupt disabled
1 = Interrupt requested when RTIF is set
Bits [5:4] — See 13.2 Pulse Accumulator Registers, page .
Bits [3:2] — Not implemented. Reads always return zero and writes have no effect.
PR[1:0] — Timer Prescaler Select
Determines the main timer prescale factor as shown in Table 31. See Table 26 for specific frequencies.
Table 31 Main Timer Prescale Control
PR[1:0]0 00 11 01 1
Prescaler
14816
TFLG2 — Timer Interrupt Flag 2 $x025
Bit 7TOFRESET:06RTIF05PAOVF04PAIF0300200100Bit 000Bits in this register indicate when certain timer system events have occurred. Coupled with the fourhigh-order bits of TMSK2, the bits of TFLG2 allow the timer subsystem to operate in either a polled orinterrupt driven system. Each bit of TFLG2 corresponds to a bit in TMSK2 in the same position.Bits in TFLG2 are cleared by writing a one to the corresponding bit positions.TOF — Timer Overflow Flag
Set when TCNT rolls over from $FFFF to $0000.
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RTIF — Real-Time Interrupt Flag
Set periodically at a rate based on bits RTR[1:0] in the PACTL register.Bits [5:4] — See 13.2 Pulse Accumulator Registers, page 65.
Bits [3:0] — Not implemented. Reads always return zero and writes have no effect.PACTL — Pulse Accumulator Control
Bit 70RESET:06PAEN05PAMOD04PEDGE03002I4/O501RTR10Bit 0RTR00$x026
Bit 7 — Not implemented. Reads always return zero and writes have no effect.Bits [6:4] — See 13.2 Pulse Accumulator Registers, page 65.
Bit 3 — Not implemented. Reads always return zero and writes have no effect.I4/O5 — Configure TI4/O5 Register for IC or OC
0 = OC5 function enabled1 = IC4 function enabled
RTR[1:0] — RTI Interrupt Rate Selects
These two bits select one of four rates for the real-time interrupt circuit, as shown in Table 32.
Table 32 Real-Time Interrupt Periods
E-Clock Frequency1 MHz2 MHz3 MHz4 MHz5 MHz6 MHzAny E
RTR [1:0] = %00
8.192 ms4.906 ms2.731 ms2.048 ms1.638 ms1.366 ms213/E
RTR [1:0] = 0116.384 ms8.192 ms5.461 ms4.096 ms3.277 ms2.731 ms214/E
RTR [1:0] = 1032.768 ms16.384 ms10.923 ms8.192 ms6.554 ms5.461 ms215/E
RTR [1:0] = 1165.536 ms32.768 ms21.845 ms16.384 ms13.107 ms10.923 ms216/E
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13 Pulse Accumulator
The pulse accumulator can be used either to count events or measure the duration of a particular event.In event counting mode, the pulse accumulator’s 8-bit counter increments each time a specified edgeis detected on the pulse accumulator input pin, PA7. The maximum clocking rate for this mode is the E-clock divided by two. In gated time accumulation mode, an internal clock increments the 8-bit counterat a rate of E-clock ÷ while the input at PA7 remains at a predetermined logic level.13.1 Pulse Accumulator Block Diagram
1INTERRUPTREQUESTS2PAOVFPAI EDGEE ÷ CLOCK(FROM MAIN TIMER)PAEN 2:1MUXCLOCKPAENPAOVIPAIIPAIFTMSK2INTERRUPT ENABLESTFLG2STATUS FLAGSOVERFLOWPA7/PAI/OC1INPUT BUFFER&EDGE DETECTIONPACNT 8-BIT COUNTERENABLEOUTPUTBUFFERFROMMAIN TIMEROC1FROMDDRAPAMODPEDGEPAENPACTLCONTROLINTERNAL DATA BUS Figure 18 Pulse Accumulator Block Diagram
13.2 Pulse Accumulator Registers
TMSK2 — Timer Interrupt Mask 2 $x024
Bit 7TOIRESET:06RTII05PAOVI04PAII03002001PR10Bit 0PR00Bits [7:4] in TMSK2 correspond bit for bit with flag bits in TFLG2. Setting any of these bits enables thecorresponding interrupt source.
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Bits[7:6] — See 12.2 Timer Registers, page 62.
PAOVI — Pulse Accumulator Overflow Interrupt Enable
0 = Pulse accumulator overflow interrupt disabled1 = Interrupt requested when PAOVF in TFLG2 is setPAII — Pulse Accumulator Interrupt Enable
0 = Pulse accumulator interrupt disabled
1 = Interrupt requested when PAIF in TFLG2 is set
Bits [3:2] — Not implemented. Reads always return zero and writes have no effect.Bits [1:0] — See 12.2 Timer Registers, page 62.TFLG2 — Timer Interrupt Flag 2
Bit 7TOFRESET:06RTIF05PAOVF04PAIF0300200100Bit 000$x025
Bits in TFLG2 are cleared by writing a one to the corresponding bit positions.Bits [7:6] — See 12.2 Timer Registers, page 62.PAOVF — Pulse Accumulator Overflow Flag
Set when PACNT rolls over from $FF to $00
PAIF — Pulse Accumulator Input Edge Flag
Set each time a selected active edge is detected on the PAI input line
Bits [3:0] — Not implemented. Reads always return zero and writes have no effect.PACTL — Pulse Accumulator Control
Bit 70RESET:06PAEN05PAMOD04PEDGE03002I4/O501RTR10Bit 0RTR00$x026
Bit 7 — Not implemented. Reads always return zero and writes have no effect.PAEN — Pulse Accumulator System Enable
0 = Pulse accumulator disabled1 = Pulse accumulator enabledPAMOD — Pulse Accumulator Mode
0 = Event counter
1 = Gated time accumulation
PEDGE — Pulse Accumulator Edge Control
This bit has different meanings depending on the state of the PAMOD bit, as shown in Table 33.
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Table 33 Pulse Accumulator Edge Control
PAMOD
0011
PEDGE0101
Action on Clock
PAI falling edge increments the counter.PAI rising edge increments the counter.A zero on PAI inhibits counting.A one on PAI inhibits counting.
Bit 3 — Not implemented. Reads always return zero and writes have no effect.Bits [2:0] — See 12.2 Timer Registers, page 63.PACNT — Pulse Accumulator Count
Bit 7Bit 7RESET:U66U55U44U33U22U11UBit 0Bit 0U$x027
U = Unaffected by reset
This eight-bit read/write register contains the count of external input events at the PAI input, or the ac-cumulated count. The PACNT is readable even if PAI is not active in gated time accumulation mode.The counter is not affected by reset and can be read or written at any time. Counting is synchronizedto the internal PH2 clock so that incrementing and reading occur during opposite half cycles.
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