RT9173D
Cost-Effective, Peak 3A Sink/Source Bus Termination Regulator
General Description
The RT9173D is a simple, cost-effective and high-speedlinear regulator designed to generate termination voltagein double data rate (DDR) memory system to comply withthe JEDEC SSTL_2 and SSTL_18 or other specificinterfaces such as HSTL, SCSI-2 and SCSI-3 etc. devicesrequirements. The regulator is capable of actively sinkingor sourcing continuous 2A or up to 3A transient peakcurrent while regulating an output voltage to within 40mV.The output termination voltage cab be tightly regulated totrack 1/2VDDQ by two external voltage divider resistors orthe desired output voltage can be pro-grammed by externallyforcing the REFEN pin voltage.
The RT9173D also incorporates a high-speed differentialamplifier to provide ultra-fast response in line/load transient.Other features include extremely low initial offset voltage,excellent load regulation, current limiting in bi-directionsand on-chip thermal shut-down protection.
The RT9173D are available in the SOP-8 (Exposed Pad)surface mount packages.
Features
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Ideal for DDR-I, DDR-II and DDR-III VTT ApplicationsSink and Source Current`2A Continuous Current
`Peak 3A for DDRI and DDRII`Peak 2.5A for DDRIII
Integrated Power MOSFETs
Generates Termination Voltage for SSTL_2,SSTL _18, HSTL, SCSI-2 and SCSI-3 InterfacesHigh Accuracy Output Voltage at Full-LoadOutput Adjustment by Two External ResistorsLow External Component Count
Shutdown for Suspend to RAM (STR) Functionalitywith High-Impedance OutputCurrent Limiting ProtectionOn-Chip Thermal Protection
Available in SOP-8 (Exposed Pad) PackagesVIN and VCNTL No Power Sequence IssueRoHS Compliant and 100% Lead (Pb)-Free
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Applications
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Ordering Information
RT9173D Package TypeSP : SOP-8 (Exposed Pad-Option 1)Operating Temperature RangeP : Pb Free with Commercial StandardG : Green (Halogen Free with Commer- cial Standard)
Note :
Richtek Pb-free and Green products are :
`RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020.
`Suitable for use in SnPb or Pb-free soldering processes.`100% matte tin (Sn) plating.
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Desktop PCs, Notebooks, and WorkstationsGraphics Card Memory TerminationSet Top Boxes, Digital TVs, PrintersEmbedded Systems
Active Termination Buses
DDR-I, DDR-II and DDR-III Memory Systems
Pin Configurations
(TOP VIEW)
VINGNDREFENVOUT
287GND36945NCNCVCNTLNC
SOP-8 (Exposed Pad)
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RT9173D
Typical Application Circuit
VCNTL = 3.3VVIN = 2.5V/1.8V/1.5VR1VINVCNTLCINCCNTLRTT2N7002ENR2CSSRT9173DREFENVOUTGNDCOUTGND
R1 = R2 = 100kΩ, RTT = 50Ω / 33Ω / 25Ω
COUT(MIN) = 10μF (Ceramic) + 1000μF under the worst case testing conditionCSS = 1μF, CIN = 470μF (Low ESR), CCNTL = 47μF
Test Circuit
2.5V/1.8V/1.5V3.3VVIN1.25V/0.9V/0.75V
VCNTLRT9173DREFENVOUTGNDVOUT
Figure 1. Test Circuit for Typical Operating Characteristics Curves
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RT9173D
Functional Pin Description
VIN (Pin 1)
Input voltage which supplies current to the output pin.Connect this pin to a well-decoupled supply voltage. Toprevent the input rail from dropping during large loadtransient, a large, low ESR capacitor is recommended touse. The capacitor should be placed as close as possibleto the VIN pin.
GND [Pin 2, Exposed pad (9)]
Common Ground (Exposed pad is connected to GND).The GND pad area should be as large as possible andusing many vias to conduct the heat into the buried GNDplate of PCB layer.REFEN (Pin 3)
Reference voltage input and active low shutdown controlpin. Two resistors dividing down the VIN voltage on the pinto create the regulated output voltage. Pulling the pin toground turns off the device by an open-drain, such as2N7002, signal N-MOSFET.
VOUT (Pin 4)
Regulator output. VOUT is regulated to REFEN voltagethat is used to terminate the bus resistors. It is capable ofsinking and sourcing current while regulating the outputrail. To maintain adequate large signal transient response,typical value of 1000μF AL electrolytic capacitor with 10μFceramic capacitors are recommended to reduce the effectsof current transients on VOUT.VCNTL (Pin 6)
VCNTL supplies the internal control circuitry and providesthe drive voltage. The driving capability of output current isproportioned to the VCNTL. Connect this pin to 3.3V biassupply to handle large output current with at least 10μFcapacitor from this pin to GND.NC (Pin 5, 7, 8)No Internal Connect.
Function Block Diagram
VCNTL
VIN
Current LimitThermal ProtectionREFEN
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+-EAVOUT
GND
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RT9173D
Absolute Maximum Ratings (Note 1)
Input Voltage, VIN------------------------------------------------------------------------------------------------------6VzControl Voltage, VCNTL-----------------------------------------------------------------------------------------------6Vz Power Dissipation, PD @ TA = 25°C
SOP-8 (Exposed Pad)-----------------------------------------------------------------------------------------------1.33WzPackage Thermal Resistance (Note 4)
SOP-8 (Exposed Pad), θJA------------------------------------------------------------------------------------------75°C/WSOP-8 (Exposed Pad), θJC-----------------------------------------------------------------------------------------28°C/WzJunction Temperature-------------------------------------------------------------------------------------------------125°CzLead Temperature (Soldering, 10 sec.)---------------------------------------------------------------------------260°CzStorage Temperature Range----------------------------------------------------------------------------------------–65°C to 150°CzESD Susceptibility (Note 2)
HBM (Human Body Mode)------------------------------------------------------------------------------------------2kVMM (Machine Mode)--------------------------------------------------------------------------------------------------200V
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Recommended Operating Conditions (Note 3)
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Input Voltage, VIN------------------------------------------------------------------------------------------------------2.5V to 1.5V ± 3%Control Voltage, VCNTL-----------------------------------------------------------------------------------------------5V or 3.3V ± 5%Ambient Temperature Range----------------------------------------------------------------------------------------−40°C to 85°CJunction Temperature Range----------------------------------------------------------------------------------------−40°C to 125°C
Electrical Characteristics
(VIN = 2.5V/1.8V/1.5V, VCNTL = 3.3V, VREFEN = 1.25V/0.9V/0.75V, COUT = 10μF (Ceramic), TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Units Input VCNTL Operation Current Standby Current (Note 7) Output (DDR / DDR II / DDR III) Output Offset Voltage (Note 5) Load Regulation (Note 6) Protection Current limit ILIM VIN = 2.5V/1.8V/1.5V -- 125 -- 3.4 170 35 -- -- -- A °C °C Thermal Shutdown Temperature TSD 3.3V ≤ VCNTL ≤ 5V Thermal Shutdown Hysteresis REFEN Shutdown Shutdown Threshold VIH Enable VIL Shutdown 0.6 -- -- V -- -- 0.2 ΔTSD 3.3V ≤ VCNTL ≤ 5V VOS ΔVLOAD IOUT = 0A IOUT = +2A IOUT = −2A −20 -- +20 mV −20 -- +20 mV ICNTL ISTBY IOUT = 0A VREFEN < 0.2V (Shutdown), RLOAD = 180Ω -- 1 2.5 mA -- 50 90 μA
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RT9173D
Note 1. Stresses listed as the above \"Absolute Maximum Ratings\" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in theoperational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extendedperiods may remain possibility to affect device reliability.
Note 2. Devices are ESD sensitive. Handling precaution recommended.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. θJA is measured in the natural convection at TA = 25°C on a high effective thermal conductivity test board (4 Layers,
2S2P) of JEDEC 51-7 thermal measurement standard. The case point of θJC is on the expose pad for SOP-8 (ExposedPad) package.
Note 5. VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN.
Note 6. Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load
regulation in the load range from 0A to 2A.
Note 7. Standby current is the input current drawn by a regulator when the output voltage is disabled by a shutdown signal on
REFEN pin (VIL < 0.2V). It is measured with VIN = VCNTL = 5V.
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RT9173D
Typical Operating Characteristics
Output Voltage vs. Temperature
0.770.765
Output Voltage vs. Temperature
0.920.915
VIN = 1.5VVIN = 1.8VOutput Voltage (V)-50
-25
0
25
50
75
100
125
Output Voltage (V)0.760.7550.750.7450.74
0.910.9050.90.50.
-50
-25
0
25
50
75
100
125
Temperature(°C)Temperature(°C)
Output Voltage vs. Temperature
1.271.265
Shutdown Threshold vs. Temperature
0.60.55
VIN = 2.5VVCNTL = 5V, Turn OnVCNTL = 5V, Turn OffShutdown Threshold (V)Output Voltage (V)1.261.2551.251.2451.24
-50
-25
0
25
50
75
100
125
0.50.450.40.35
VCNTL = 3.3V, Turn OnVCNTL = 3.3V, Turn Off0.30.25
-50
-25
0
25
50
75
100
125
Temperature(°C)Temperature(°C)
VIN Current vs. Temperature
54.5
Vcntl Current vs. Temperature
0.60.55
VIN = 1.8V, VCNTL = 3.3VVIN = 1.8V, VCNTL = 5VVIN = 2.5V, VCNTL = 3.3VVIN = 2.5V, VCNTL = 5VVcntl Current (mA)VIN Current (mA)43.53
0.50.450.40.350.3
VIN = 1.8V, VCNTL = 3.3VVIN = 1.8V, VCNTL = 5VVIN = 2.5V, VCNTL = 3.3VVIN = 2.5V, VCNTL = 5VVIN = 1.5V, VCNTL = 5V2.52-50
-25
0
25
50
75
100
125
VIN = 1.5V, VCNTL = 5VVIN = 1.5V, VCNTL = 3.3VVIN = 1.5V, VCNTL = 3.3V-50-250255075100125
Temperature(°C)
Temperature(°C)
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RT9173D
Source Current Limit vs. Temperature
4.5
Sink Current Limit vs. Temperature
4.5
Source Current Limit (A)Sink Current Limit (A)4
3.5
VIN = 1.8V, VCNTL = 5VVIN = 1.8V, VCNTL = 3.3VVIN = 2.5V, VCNTL = 5VVIN = 2.5V,VCNTL = 3.3V4
VIN = 1.8V, VCNTL = 3.3VVIN = 2.5V, VCNTL = 3.3VVIN = 2.5V, VCNTL = 5VVIN = 1.8V, VCNTL = 5V3.5
3
VIN = 1.5V, VCNTL = 5VVIN = 1.5V, VCNTL = 3.3V3
2.52.5
VIN = 1.5V, VCNTL = 5VVIN = 1.5V, VCNTL = 3.3V2-50
-25
0
25
50
75
100
125
2-50
-25
0
25
50
75
100
125
Temperature(°C)Temperature(°C)
0.9VTT @ 2A Transient Response
Output VoltageTransient (mV)Output VoltageTransient (mV)VIN = 1.8V, VCNTL = 3.3V, VOUT = 0.9V
Sink
0.9VTT @ 2A Transient Response
VIN = 1.8V, VCNTL = 3.3V, VOUT = 0.9V
Source
40200-20210Swing Frequency : 1kHz
40200-20210
Swing Frequency : 1kHz
Output Current (A)Time (250μs/Div)
Output Current (A)Time (250μs/Div)
0.75VTT @ 2A Transient Response
Output VoltageTransient (mV)0.75VTT @ 2A Transient Response
Output VoltageTransient (mV)VIN = 1.5V, VCNTL = 3.3V, VOUT = 0.75V
Source
VIN = 1.5V, VCNTL = 3.3V, VOUT = 0.75V
Sink
40200-20210
Swing Frequency : 1kHz
40200-20210
Swing Frequency : 1kHz
Output Current (A)Time (250μs/Div)
Output Current (A)Time (250μs/Div)
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RT9173D
1.25VTT @ 2A Transient Response
Output VoltageTransient (mV)Output VoltageTransient (mV)VIN = 2.5V, VCNTL = 3.3V, VOUT = 1.25V
Sink
1.25VTT @ 2A Transient Response
VIN = 2.5V, VCNTL = 3.3V, VOUT = 1.25V
Source
40200-20210
Swing Frequency : 1kHz
40200-20210Swing Frequency : 1kHz
Output Current (A)Time (250μs/Div)
Output Current (A)Time (250μs/Div)
Output Short-Circuit Protection
12Output Short Circuit (A)VIN = 1.5V, VCNTL = 3.3V
Sink
Output Short-Circuit Protection
12Output Short Circuit (A)VIN = 1.5V, VCNTL = 3.3V
Source
1082010820Time (1ms/Div)Time (1ms/Div)
Output Short-Circuit Protection
VIN = 1.8V, VCNTL = 3.3V
Sink
Output Short-Circuit Protection
VIN = 1.8V, VCNTL = 3.3V
Source
12Output Short Circuit (A)Output Short Circuit (A)121082010820Time (1ms/Div)Time (1ms/Div)
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RT9173D
Output Short-Circuit Protection
12Output Short Circuit (A)VIN = 2.5V, VCNTL = 3.3V
Sink
Output Short-Circuit Protection
VIN = 2.5V, VCNTL = 3.3V
Source
12Output Short Circuit (A)1082010820Time (1ms/Div)
Time (1ms/Div)
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RT9173D
Application Information
Consideration while designs the resistance of voltagedivider
Make sure the sinking current capability of pull-down NMOSif the lower resistance was chosen so that the voltage onVREFEN is below 0.2V.
In addition, the capacitor and voltage divider form the low-pass filter. There are two reasons doing this design; one isfor output voltage soft-start while another is for noiseimmunity.
How to reduce power dissipation on Notebook PC orthe dual channel DDR SDRAM application?
In notebook application, using RichTek's Patent“Distributed Bus Terminator Topology” with choosingRichTek's product is encouraged.
Distributed Bus Terminating Topology
Terminator Resistor
General Regulator
The RT9173D could also serves as a general linearregulator. The RT9173D accepts an external referencevoltage at REFEN pin and provides output voltage regulatedto this reference voltage as shown in Figure 3, whereVOUT = VEXT x R2/(R1+R2)
As other linear regulator, dropout voltage and thermal issueshould be specially considered. Figure 4 and 5 show theRDS(ON) over temperature of RT9173D in PSOP-8 (ExposedPad) package. The minimum dropout voltage could beobtained by the product of RDS(ON) and output current. Forthermal consideration, please refer to the relative sections.
RDS(ON) vs. Temperature
0.40
VCNTL = 3.3V0.350.300.250.200.150.10
-50
-25
0
25
50
75
100
125
BUS(0)BUS(1)
R1VOUTR2R3R4REFENR5R6BUS(6)
RT9173DVOUTR7R8BUS(8)
R9BUS(9)BUS(7)
RT9173DBUS(2)BUS(3)BUS(4)BUS(5)
RDS(ON) (Ω)R0Temperature(°C)
Figure 4
RDS(ON) vs. Temperature
0.40
R(2N)R(2N+1)BUS(2N)
VCNTL = 5V0.35
BUS(2N+1)
VEXT
VCNTLVINVOUT
RDS(ON) (Ω)Figure 2
0.300.250.200.150.10
-50
-25
0
25
50
75
100
125
R1RT9173DREFENVOUTGNDR2Temperature(°C)
Figure 3
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Figure 5
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RT9173D
Input Capacitor and Layout Consideration
Place the input bypass capacitor as close as possible tothe RT9173D. A low ESR capacitor larger than 470uF isrecommended for the input capacitor. Use short and widetraces to minimize parasitic resistance and inductance.Inappropriate layout may result in large parasitic inductanceand cause undesired oscillation between RT9173D and thepreceding power converter.Thermal Consideration
RT9173D regulators have internal thermal limiting circuitrydesigned to protect the device during overload conditions.For continued operation, do not exceed maximum operationjunction temperature 125°C. The power dissipationdefinition in device is:
PD = (VIN - VOUT) x IOUT + VIN x IQ
The maximum power dissipation depends on the thermalresistance of IC package, PCB layout, the rate ofsurroundings airflow and temperature difference betweenjunction to ambient. The maximum power dissipation canbe calculated by following formula:PD(MAX) = ( TJ(MAX) -TA ) /θJA
Where TJ(MAX) is the maximum operation junctiontemperature 125°C, TA is the ambient temperature and theθJA is the junction to ambient thermal resistance. Thejunction to ambient thermal resistance (θJA is layoutdependent) for SOP-8 package (Exposed Pad) is 75°C/Won standard JEDEC 51-7 (4 layers, 2S2P) thermal testboard. The maximum power dissipation at TA = 25°C canbe calculated by following formula:PD(MAX) = (125°C - 25°C) / 75°C/W = 1.33W
Figure 6 show the package sectional drawing of SOP-8(Exposed Pad). Every package has several thermaldissipation paths. As show in Figure 7, the thermalresistance equivalent circuit of SOP-8 (Exposed Pad). Thepath 2 is the main path due to these materials thermalconductivity. We define the exposed pad is the case pointof the path 2.
The thermal resistance θJA of SOP-8 (Exposed Pad) isdetermined by the package design and the PCB design.However, the package design has been decided. If possible,it's useful to increase thermal performance by the PCBdesign. The thermal resistance can be decreased byadding copper under the expose pad of SOP-8 package.About PCB layout, the Figure 8 show the relation betweenthermal resistance θJA and copper area on a standardJEDEC 51-7 (4 layers, 2S2P) thermal test board atTA = 25°C.We have to consider the copper couldn't stretchinfinitely and avoid the tin overflow. We use the “dog-bone”copper patterns on the top layer as Figure 9.
As shown in Figure 10, the amount of copper area to whichthe SOP-8 (Exposed Pad) is mounted affects thermalperformance. When mounted to the standard SOP-8(Exposed Pad) pad of 2 oz. copper (Figure 10.a), θJA is75°C/W. Adding copper area of pad under the SOP-8(Exposed Pad) (Figure 10.b) reduces the θJA to °C/W.Even further, increasing the copper area of pad to 70mm2(Figure 10.e) reduces the θJA to 49°C/W.
JunctionAmbient
Molding CompoundGold LineLead FrameDie PadCase (Exposed Pad)Figure 6. SOP-8 (Exposed Pad) Package Sectional
Drawing
RGOLD-LINEpath 1RDIERLEAD FRAMERPCBRDIE-ATTACHRDIE-PADpath 2RPCBAmbientCase(Exposed Pad)RMOLDING-COMPOUNDpath 3Figure 7. Thermal Resistance Equivalent Circuit
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RT9173D
θJA vs. Copper Area
1009080
θJA (°C/W)7060504030
0
10
20
30
40
50
2
Figure 10 (b). Copper Area = 10mm2, θJA = °C/W
6070
Copper Area (mm)
Figure 8
Exposed PadFigure 10 (c). Copper Area = 30mm2, θJA = 54°C/W
W≦2.28mmFigure 9.Dog-Bone layoutFigure 10 (d). Copper Area = 50mm2, θJA = 51°C/W
Figure 10 (a). Minimum Footprint, θJA = 75°C/WFigure 10 (e). Copper Area = 70mm2, θJA = 49°C/W
Figure 10. Thermal Resistance vs. Different Cooper Area
Layout Design
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RT9173D
Outline Information
AH
M
EXPOSED THERMAL PAD(Bottom of Package)
YJXB
F
CI
DSymbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 4.801 5.004 0.1 0.197 B 3.810 4.000 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.510 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.000 0.152 0.000 0.006 J 5.791 6.200 0.228 0.244 M 0.406 1.270 0.016 0.050 Option 1 X 2.000 2.300 0.079 0.091 Y 2.000 2.300 0.079 0.091 X 2.100 2.500 0.083 0.098 Y 3.000 3.500 0.118 0.138 Option 2 8-Lead SOP (Exposed Pad) Plastic Package
Richtek Technology Corporation
Headquarter
5F, No. 20, Taiyuen Street, Chupei CityHsinchu, Taiwan, R.O.C.
Tel: (8863)55267 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing)
8F, No. 137, Lane 235, Paochiao Road, Hsintien CityTaipei County, Taiwan, R.O.C.
Tel: (8862)191466 Fax: (8862)191465Email: marketing@richtek.com
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